Abstract: A semiconductor storage device is provided. The semiconductor storage device includes a first voltage supply line coupled to a gate electrode of a first memory transistor through a first transistor, a first signal supply line coupled to a gate electrode of the first transistor, a first capacitor coupled to the gate electrode of the first memory transistor, and a first wiring coupled between the gate electrode of the first memory transistor and the first transistor through the first capacitor. In a write operation on the first memory transistor, at a second timing after a first timing, a voltage present on the first signal supply line decreases from a second voltage to a fourth voltage lower than the second voltage, and at a third timing after the second timing, the voltage present on the first wiring increases from a third voltage to a fifth voltage higher than the third voltage.

Abstract: A semiconductor storage device includes: a first voltage supply line coupled to a gate electrode of a first memory transistor through a first transistor; a first signal supply line coupled to a gate electrode of the first transistor; a first capacitor coupled to the gate electrode of the first memory transistor; and a first wiring coupled between the gate electrode of the first memory transistor and the first transistor through the first capacitor. In a write operation on the first memory transistor, at a second timing after a first timing, a voltage present on the first signal supply line decreases from a second voltage to a fourth voltage lower than the second voltage; and at a third timing after the second timing, the voltage present on the first wiring increases from a third voltage to a fifth voltage higher than the third voltage.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

Abstract: A semiconductor memory device includes a substrate; a first impurity region of a first conductive type; a second impurity region of the first conductivity type apart from the first impurity region in a first direction; a first transistor including a first electrode disposed between the first impurity region and the second impurity region; a third impurity region of the first conductive type apart from the first impurity region in a second direction that crosses the first direction; a fourth impurity region of the first conductive type apart from the third impurity region in the first direction; a second transistor including a second electrode disposed between the third impurity region and the fourth impurity region. The semiconductor memory device includes an active region of the first conductive type between the first transistor and the second transistor.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

Abstract: A semiconductor memory device includes a substrate; a first impurity region of a first conductive type; a second impurity region of the first conductivity type apart from the first impurity region in a first direction; a first transistor including a first electrode disposed between the first impurity region and the second impurity region; a third impurity region of the first conductive type apart from the first impurity region in a second direction that crosses the first direction; a fourth impurity region of the first conductive type apart from the third impurity region in the first direction; a second transistor including a second electrode disposed between the third impurity region and the fourth impurity region. The semiconductor memory device includes an active region of the first conductive type between the first transistor and the second transistor.

Abstract: An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.

Abstract: An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.

Abstract: According to one embodiment, a semiconductor memory device includes first-third conductive layers, a semiconductor layer, a resistance change layer and a metal-containing layer. The second conductive layer is separated from the first conductive layer in a first direction. The semiconductor layer is provided between the first and the second conductive layers. The third conductive layer is arranged with the first semiconductor layer in a direction crossing the first direction. The first resistance change layer is provided between the first semiconductor layer and the first conductive layer. The first metal-containing layer is provided between the first resistance change layer and the first conductive layer. The first conductive layer extends in a second direction crossing the first direction. The second conductive layer extends in a third direction crossing the first direction and crossing the second direction. The third conductive layer extends in a direction crossing the first direction.

Abstract: A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

Abstract: A semiconductor device according to an embodiment includes a first transistor and a second transistor. The first transistor is connected to a first wiring through a wiring plug made of a material having a first resistance value smaller than a predetermined value. In addition, at least any one of a drain and a source of the second transistor is connected to a second wiring through a polysilicon plug made of a material having a second resistance value larger than the first resistance value.

Abstract: A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

Abstract: The present invention is directed to, for example, an oligosaccharide having at an end thereof a 4-position halogenated galactose residue represented by formula (I): (wherein X represents a halogen atom, and R represents a monosaccharide, an oligosaccharide, or a carrier), a transferase inhibitor containing the oligosaccharide, and a method for inhibiting sugar chain elongation reaction in the presence of glycosyltransferase, the method including employing the inhibitor. The invention also provides a method for producing a 4-position halogenated galactose sugar nucleotide represented by formula (II): (wherein each of R1 to R3 represents a hydroxyl group, an acetyl group, a halogen atom, or a hydrogen atom; X represents a halogen atom; and M represents a hydrogen ion or a metal ion), wherein the method employs bacterium-derived galactokinase and bacterium-derived hexose-1-phosphate uridylyltransferase.

Abstract: The present invention provides a method for enzymatically producing uridine 5?-diphospho-N-acetylgalactosamine (UDP-GalNAc) (which is an important substrate for oligosaccharide synthesis) from uridine 5?-triphosphate (UTP) and N-acetylgalactosamine 1-phosphate (GalNAc 1-P), the method including using, as an enzyme, uridine 5?-diphospho-N-acetylglucosamine pyrophosphorylase (UDP-GlcNAc pyrophosphorylase) derived from a microorganism (exclusive of a pathogenic microorganism). The GalNAc 1-P employed can be prepared from N-acetylgalactosamine and a phosphate donor in a reaction system by use of N-acetylgalactosamine kinase. According to the present invention, uridine 5?-diphospho-N-acetylgalactosamine can be efficiently produced by use of a relatively inexpensive substrate.

Abstract: A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed.

Abstract: The present invention is directed to, for example, an oligosaccharide having at an end thereof a 4-position halogenated galactose residue represented by formula (I): (wherein X represents a halogen atom, and R represents a monosaccharide, an oligosaccharide, or a carrier), a transferase inhibitor containing the oligosaccharide, and a method for inhibiting sugar chain elongation reaction in the presence of glycosyltransferase, the method including employing the inhibitor. The invention also provides a method for producing a 4-position halogenated galactose sugar nucleotide represented by formula (II): (wherein each of R1 to R3 represents a hydroxyl group, an acetyl group, a halogen atom, or a hydrogen atom; X represents a halogen atom; and M represents a hydrogen ion or a metal ion), wherein the method employs bacterium-derived galactokinase and bacterium-derived hexose-1-phosphate uridylyltransferase.

Abstract: The invention provides a process for producing 2?-deoxyguanosine, characterized in that the process includes reacting one compound selected from the group consisting of guanosine, guanosine 5?-monophosphate, and 2-amino-6-substituted purine with 2?-deoxynucleoside in the presence of nucleoside deoxyribosyl transferase and a hydrolase. According to the process of the present invention, 2?-deoxyguanosine can be synthesized efficiently from inexpensive and easily available starting materials. Since no guanosine, which disturbs purification, is virtually present in a reaction mixture, isolation and purification of 2?-deoxyguanosine can be performed in a very simple manner. Thus, the process for producing 2?-deoxyguanosine is practical.

Abstract: A process for producing uridine diphosphate-N-acetylglucosamine (UDPAG) from uridylic acid (UMP) and N-acetylglucosamine by use of microorganism cells, characterized by adding N-acetylglucosamine kinase thereto. According to the present invention, UDPAG can be efficiently produced even when N-acetylglucosamine is used as a substrate.