Patents by Inventor Kiyoshi Onuki

Kiyoshi Onuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996132
    Abstract: A semiconductor device includes a first transistor one of a source and a drain of which is electrically connected to a first wiring for reading data; a second transistor one of a source and a drain of which is electrically connected to a gate of the first transistor and the other of the source and the drain of which is electrically connected to a second wiring for writing the data; and a third transistor one of a source and a drain of which is electrically connected to the gate of the first transistor and the other of the source and the drain of which is electrically connected to a capacitor for retaining electric charge corresponding to the data, and the third transistor includes a metal oxide in a channel formation region.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: May 28, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 11984152
    Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 14, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki
  • Patent number: 11961916
    Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Kiyoshi Kato, Tomoaki Atsumi, Shunpei Yamazaki
  • Patent number: 8205014
    Abstract: A tuning plan for a configuration of a resource of a storage system 5 is generated by acquiring configuration information of the resource of the storage system 5, and acquiring performance data of a reference value exceeding resource that is the resource having a utilization rate exceeding a preset reference value, and performance data of an analysis target resource that is a resource having a certain relationship with a reference value exceeding resource, and obtaining correlation degree between the reference value exceeding resource and the analysis target resources based on the performance data of the reference value exceeding resource and the performance data of the analysis target resources, and selecting a correlated analysis target resource that is the analysis target resource determined to have correlation with the reference value exceeding resource from the obtained correlation degree, and by calculating an average resource utilization rate of a resource group in a predetermined range on the basis of
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: June 19, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Kiyoshi Onuki
  • Publication number: 20100325314
    Abstract: A tuning plan for a configuration of a resource of a storage system 5 is generated by acquiring configuration information of the resource of the storage system 5, and acquiring performance data of a reference value exceeding resource that is the resource having a utilization rate exceeding a preset reference value, and performance data of an analysis target resource that is a resource having a certain relationship with a reference value exceeding resource, and obtaining correlation degree between the reference value exceeding resource and the analysis target resources based on the performance data of the reference value exceeding resource and the performance data of the analysis target resources, and selecting a correlated analysis target resource that is the analysis target resource determined to have correlation with the reference value exceeding resource from the obtained correlation degree, and by calculating an average resource utilization rate of a resource group in a predetermined range on the basis of
    Type: Application
    Filed: February 2, 2009
    Publication date: December 23, 2010
    Inventor: Kiyoshi Onuki