Patents by Inventor Kiyoshi Ouchi

Kiyoshi Ouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8310647
    Abstract: Disorder in the initial orientation (pretilt angle) and active orientation of liquid crystal molecules associated with higher resolution can be reduced to achieve high image quality displays. A layer having a drive element is bonded into an adhesive layer above color filters provided on the inner surface of a rear panel. The layer with the drive element, a drive electrode (pixel electrode), and a counter electrode are buried in the adhesive layer, so that the surface on the liquid crystal layer side is smooth. An orientation film is formed on the smooth surface to have a liquid crystal orientation control capability (orientation capability). A front panel includes a transparent substrate formed of glass or resin, with a smooth surface on the liquid crystal layer side. An orientation film is formed on the smooth surface of the front panel also to have liquid crystal orientation control capability (orientation capability).
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: November 13, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiko Muneyoshi, Kiyoshi Ouchi
  • Publication number: 20120127403
    Abstract: Disorder in the initial orientation (pretilt angle) and active orientation of liquid crystal molecules associated with higher resolution can be reduced to achieve high image quality displays. A layer having a drive element is bonded into an adhesive layer above color filters provided on the inner surface of a rear panel. The layer with the drive element, a drive electrode (pixel electrode), and a counter electrode are buried in the adhesive layer, so that the surface on the liquid crystal layer side is smooth. An orientation film is formed on the smooth surface to have a liquid crystal orientation control capability (orientation capability). A front panel includes a transparent substrate formed of glass or resin, with a smooth surface on the liquid crystal layer side. An orientation film is formed on the smooth surface of the front panel also to have liquid crystal orientation control capability (orientation capability).
    Type: Application
    Filed: January 6, 2012
    Publication date: May 24, 2012
    Applicants: Panasonic Liquid Crystal Display Co., Ltd., Hitachi Displays, Ltd.
    Inventors: Takahiko Muneyoshi, Kiyoshi Ouchi
  • Publication number: 20120025213
    Abstract: A flat panel display is manufactured by mass production and easily stored and transported at low cost. Provided is a thin film semiconductor substrate which faces a plastic substrate 7 and is combined with the plastic substrate 7 so as to be a flat panel display. Single-board-like insulating substrates 4 each of which has a thin film semiconductor array 3 are continuously bonded onto a lengthy plastic film 2. An apparatus is also provided for manufacturing the thin film semiconductor substrate which faces the plastic substrate 7 and is combined with the plastic substrate 7 so as to be the flat panel display.
    Type: Application
    Filed: March 27, 2009
    Publication date: February 2, 2012
    Inventors: Shigeyoshi Otsuki, Toshimasa Eguchi, Masatoshi Naka, Kazushige Takechi, Kiyoshi Ouchi
  • Patent number: 7902003
    Abstract: An image display device capable of high-resolution and smooth moving image display, equipped with TFTs in an n-type (or p-type) semiconductor layer with a high on-off ratio and a low resistance. In polysilicon crystallization by laser annealing, an n-type (or p-type) semiconductor layer with a low resistance is produced by performing the following processes in order: implanting nitrogen (N) ions into an amorphous silicon precursor semiconductor film; laser crystallization; implanting n-type (or p-type) dopant ions; and annealing for dopant activation. When fabricating TFTs, this low-resistance semiconductor layer is used to form a source and a drain. Since C, N, and O impurities decrease the mobility of the TFTs, polysilicon is used in which the contaminants concentrations meet the following conditions: carbon concentration ?3×1019 cm?3, nitrogen concentration ?5×1017 cm?3, and oxygen concentration ?3×1019 cm?3.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 8, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Kiyoshi Ouchi, Mutsuko Hatano, Takeshi Sato, Mitsuharu Tai
  • Publication number: 20080290344
    Abstract: An image display device manufactured by using a polycrystalline semiconductor film. The polycrystalline semiconductor film is composed of crystal grains with a region free from crystal grain boundaries of at least 2 ?m in width and at least 3 ?m in length, small crystal grain boundary groups each composed of three or more crystal grain boundaries arranged substantially in parallel to each other and with an interval of not greater than 100 ?m are included in a part of the region, and the small crystal grain boundary groups are partially eliminated.
    Type: Application
    Filed: May 29, 2008
    Publication date: November 27, 2008
    Inventors: Mitsuharu TAI, Mutsuko HATANO, Takeshi SATO, Seongkee PARK, Kiyoshi OUCHI
  • Patent number: 7384810
    Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: June 10, 2008
    Assignee: Hitachi Displays, Ltd.
    Inventors: Mitsuharu Tai, Mutsuko Hatano, Takeshi Sato, Seongkee Park, Kiyoshi Ouchi
  • Publication number: 20080079874
    Abstract: Disorder of the initial orientation (pretilt angle) of liquid crystal molecules and disorder of the active orientation of the liquid crystal molecules associated with higher resolution can be reduced to achieve high image quality display. A layer in which a drive element is configured is bonded into an adhesive layer above color filters for a plurality of colors provided on the inner surface of a rear panel. The layer in which the drive element is configured, a drive electrode (pixel electrode), a counter electrode, and the like are buried in the adhesive layer, so that the surface on the liquid crystal layer side is a smooth surface. An orientation film is formed on the smooth surface, so that a liquid crystal orientation control capability (orientation capability) is imparted thereto. A front panel includes a transparent substrate formed of a glass plate or a resin sheet, the surface of which on the liquid crystal layer side is a smooth surface.
    Type: Application
    Filed: September 26, 2007
    Publication date: April 3, 2008
    Inventors: Takahiko Muneyoshi, Kiyoshi Ouchi
  • Publication number: 20070155070
    Abstract: An image display device capable of high-resolution and smooth moving image display, equipped with TFTs in an n-type (or p-type) semiconductor layer with a high on-off ratio and a low resistance. In polysilicon crystallization by laser annealing, an n-type (or p-type) semiconductor layer with a low resistance is produced by performing the following processes in order: implanting nitrogen (N) ions into an amorphous silicon precursor semiconductor film; laser crystallization; implanting n-type (or p-type) dopant ions; and annealing for dopant activation. When fabricating TFTs, this low-resistance semiconductor layer is used to form a source and a drain. Since C, N, and O impurities decrease the mobility of the TFTs, polysilicon is used in which the contaminants concentrations meet the following conditions: carbon concentration ?3×1019 cm?3, nitrogen concentration ?5×1017 cm?3, and oxygen concentration ?3×1019 cm?3.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 5, 2007
    Inventors: Kiyoshi OUCHI, Mutsuko Hatano, Takeshi Sato, Mitsuharu Tai
  • Publication number: 20060267011
    Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 30, 2006
    Inventors: Mitsuharu Tai, Mutsuko Hatano, Takeshi Sato, Seongkee Park, Kiyoshi Ouchi
  • Patent number: 6881639
    Abstract: The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: April 19, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Kiyoshi Ouchi, Tomonori Tanoue
  • Patent number: 6728283
    Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided. The semiconductor laser device has a first semiconductor layer 5 and second semiconductor layers 4, the layer 5 and the layers 4 forming a type-II heterojunction structure, in which an energy of conduction band edge of said first conductor layer 5 is larger than the energy of conduction band of said second semiconductor layers 4. The device has third semiconductor layers 6 as barrier layers formed on both sides of said type-II heterojunction structure.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tomoyoshi Mishima
  • Publication number: 20030186509
    Abstract: The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.
    Type: Application
    Filed: February 26, 2003
    Publication date: October 2, 2003
    Inventors: Kazuhiro Mochizuki, Kiyoshi Ouchi, Tomonori Tanoue
  • Publication number: 20030132496
    Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.
    Type: Application
    Filed: November 19, 2002
    Publication date: July 17, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Akihisa Terano, Hiroshi Ohta, Kiyoshi Ouchi, Tomoyoshi Mishima
  • Publication number: 20030086461
    Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided.
    Type: Application
    Filed: November 5, 2002
    Publication date: May 8, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tomoyoshi Mishima
  • Publication number: 20030062538
    Abstract: A semiconductor device with improved heat radiation characteristics that is formed by employing a lattice-mismatched system semiconductor thin-film crystal layered product. In fabricating an HBT on a semi-insulating GaAs substrate, the HBT comprised of a material system lattice-matched to InP that is different from the substrate in the lattice constant, a structure is employed that comprises alloy compound semiconductor layers with thermal resistivities that increase with increasing lattice constant (e.g., InxGa1−xAs) and alloy compound semiconductor layers with thermal resistivities that decrease with increasing lattice constant (e.g., InyGa1−yP) as a lattice-strain-relaxed buffer layer. By using the above-mentioned lattice-strain-relaxed buffer layer, the thermal resistivity of the buffer layer can be reduced compared to a lattice-strain-relaxed buffer layer consisting of only InxGa1−xAs materials and a lattice-strain-relaxed buffer layer consisting of only InyGa1−yP materials.
    Type: Application
    Filed: May 15, 2002
    Publication date: April 3, 2003
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tohru Oka, Tomoyoshi Mishima
  • Patent number: 6510869
    Abstract: The present invention provides a ball check valve in which the area of a channel leading from a ball chamber to a discharge-side channel can be increased, and the adhesion of a ball to a valve seat surface is satisfactory even when the ball check valve is used in a horizontal posture. In the ball check valve having a ball (3) movably housed in a ball chamber (2) provided inside a valve casing (1), two or more rail-like ridges (13) protruding toward the interior of the ball chamber to guide the ball (3) are provided on a peripheral wall (10) demarcating the ball chamber (2). Furthermore, valve seats (20a, 20b) constituted separately from the valve casing (1) are mounted, respectively, on the inflow side and the discharge side of the valve casing (1).
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: January 28, 2003
    Assignee: Ebara Corporation
    Inventors: Kiyoshi Ouchi, Masaru Sato
  • Publication number: 20020149032
    Abstract: In order to provide a high-output field effect transistor having adopted such a structure that a heterointerface between an arsenic compound and a phosphoric compound does not influence the property of a device, and a high-output obtainable high frequency module equipped with MMIC fabricated using the field effect transistor, the field effect transistor having at least a channel layer through which electrons travel, an electron supply layer for supplying electrons to the channel layer, and a buffer layer for flattening the channel layer is provided with an inserted layer larger in bandgap than the buffer layer, which is formed between the buffer layer and the channel layer. This structure can be realized by, for example, achieving the substrate side of the channel layer as an InP layer, the inserted layer as InAlP layer, and the buffer layer as an InAlAs layer respectively.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 17, 2002
    Inventors: Kiyoshi Ouchi, Tomoyoshi Mishima
  • Patent number: 5055006
    Abstract: Disclosed is a submerged motor pump of the type in which a motor is installed inside an outer casing so as to define an annular passage therebetween and a pumped liquid is discharged to the outside through the annular passage while cooling the entire periphery of the motor. The outer casing is formed using a resilient material and is retained at its upper and lower ends by rigid members. Accordingly, the outer casing is deformable in the radial direction so as to absorb external force, for example, impact force, which may be applied thereto during transportation.
    Type: Grant
    Filed: February 7, 1989
    Date of Patent: October 8, 1991
    Assignee: Ebara Corporation
    Inventors: Makoto Kobayashi, Kiyoshi Ouchi, Shinji Nishimori, Tsuyoshi Maeda, Yoshio Miyake
  • Patent number: 4934914
    Abstract: A portable motor pump of the type in which a pump section driven by a motor is installed inside a liquid chamber, with a discharge port of the pump section being opened into the liquid chamber, and in which water which is to be pumped is led from the outside of the liquid chamber to a suction port of the pump section and the pumped water is discharged from the liquid chamber to the outside is disclosed. The liquid chamber is defined by a motor pump body, a pump outer casing outwardly spaced from and surrounding the motor pump body, a motor head cover covering an upper opening of the pump outer casing and a bottom plate covering a lower opening of the pump outer casing. A circulating water suction port for self-priming of the motor pump is opened into the liquid chamber. A suction port which communicates with the suction port of the pump section and a discharge port for discharging the pumped water to the outside are provided in the motor head cover.
    Type: Grant
    Filed: July 29, 1988
    Date of Patent: June 19, 1990
    Assignee: Ebara Corporation
    Inventors: Makoto Kobayashi, Kiyoshi Ouchi, Shinji Nishimori, Tsuyoshi Maeda, Yoshio Miyake
  • Patent number: 4626721
    Abstract: A submergible motor pump assembly with easy access to any part of the assembly by dismantling minimum elements, i.e. without requiring disassembly of the whole and without requiring discharge of lubricating oil for a mechanical seal. Also, plural balance holes are provided in the main plate of the impeller, and a liner ring is disposed between the main plate and the top wall of the impeller chamber, to establish the flow passage from the tip of the impeller blades through the gap between the main plate and the top wall of the chamber to the balance holes, with flow zones restricted by the liner ring. The five part input power connector includes a tapered rubber boot clamped to a plastic cap in which the terminals are further sealed in place by a resin fill.
    Type: Grant
    Filed: March 4, 1985
    Date of Patent: December 2, 1986
    Assignee: Ebara Corporation
    Inventor: Kiyoshi Ouchi