Patents by Inventor Kiyoshi Ozaki
Kiyoshi Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7187423Abstract: It is an object of the invention to provide a display and a method for repairing defects of the same in which defects such as inter-layer short-circuits and short-circuits in a single that have occurred at steps for manufacturing the display can be easily repaired to provide a good product with a probability higher than that in the related art. Laser irradiation is carried out as a first cycle of laser irradiation by forming a slit S1 in a region where a drain bus line 220 completely covers a gate bus line 218 to form a cut portion longer than the width of the gate bus line 218 adjacent to an inter-layer short-circuit 290 such that it splits an intersecting portion of the drain bus line 220 into two parts as shown in FIG. 5b. Next, as shown in FIG. 5c, slits S2 and S3 are respectively used for second and third cycles of laser irradiation to cut the drain bus line 220 at both ends of the cut portion (indicated by S1), thereby isolating the inter-layer short-circuit 290 of the drain bus line 220.Type: GrantFiled: October 19, 2004Date of Patent: March 6, 2007Assignee: Sharp Kabushiki KaishaInventors: Kiyoshi Ozaki, Tsuyoshi Kamada, Kunio Matsubara, Shinya Katoh, Yoshihisa Taguchi, Katsushige Asada, Shogo Hayashi
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Patent number: 6940579Abstract: The present invention relates to a liquid crystal display device and a defect repairing method for the same, and has an object to provide a liquid crystal display device in which a disconnection defect occurring in a storage capacitor bus line can be repaired without producing a new point defect, and a defect repairing method for the same.Type: GrantFiled: September 19, 2001Date of Patent: September 6, 2005Assignee: Sharp CorporationInventors: Kiyoshi Ozaki, Tsuyoshi Kamada, Kouji Tsukao
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Publication number: 20050078235Abstract: It is an object of the invention to provide a display and a method for repairing defects of the same in which defects such as inter-layer short-circuits and short-circuits in a single that have occurred at steps for manufacturing the display can be easily repaired to provide a good product with a probability higher than that in the related art. Laser irradiation is carried out as a first cycle of laser irradiation by forming a slit S1 in a region where a drain bus line 220 completely covers a gate bus line 218 to form a cut portion longer than the width of the gate bus line 218 adjacent to an inter-layer short-circuit 290 such that it splits an intersecting portion of the drain bus line 220 into two parts as shown in FIG. 5b. Next, as shown in FIG. 5c, slits S2 and S3 are respectively used for second and third cycles of laser irradiation to cut the drain bus line 220 at both ends of the cut portion (indicated by S1), thereby isolating the inter-layer short-circuit 290 of the drain bus line 220.Type: ApplicationFiled: October 19, 2004Publication date: April 14, 2005Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Kiyoshi Ozaki, Tsuyoshi Kamada, Kunio Matsubara, Shinya Katoh, Yoshihisa Taguchi, Katsushige Asada, Shogo Hayashi
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Patent number: 6856374Abstract: It is an object of the invention to provide a display and a method for repairing defects of the same in which defects such as inter-layer short-circuits and short-circuits in a single that have occurred at steps for manufacturing the display can be easily repaired to provide a good product with a probability higher than that in the related art. Laser irradiation is carried out as a first cycle of laser irradiation by forming a slit S1 in a region where a drain bus line 220 completely covers a gate bus line 218 to form a cut portion longer than the width of the gate bus line 218 adjacent to an inter-layer short-circuit 290 such that it splits an intersecting portion of the drain bus line 220 into two parts as shown in FIG. 5b. Next, as shown in FIG. 5c, slits S2 and S3 are respectively used for second and third cycles of laser irradiation to cut the drain bus line 220 at both ends of the cut portion (indicated by S1), thereby isolating the inter-layer short-circuit 290 of the drain bus line 220.Type: GrantFiled: July 27, 2000Date of Patent: February 15, 2005Assignee: Fujitsu Display Technologies CorporationInventors: Kiyoshi Ozaki, Tsuyoshi Kamada, Kunio Matsubara, Shinya Katoh, Yoshihisa Taguchi, Katsushige Asada, Shogo Hayashi
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Patent number: 6614494Abstract: A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film.Type: GrantFiled: May 21, 2001Date of Patent: September 2, 2003Assignee: Fujitsu Display Technologies CorporationInventors: Satoru Kawai, Kiyoshi Ozaki, Jun Inoue, Yoshio Dejima, Kenji Okamoto
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Publication number: 20030117572Abstract: A method of manufacturing a display device includes the steps of: (a) capturing an insulating granular spacer with an optical forceps apparatus which utilizes a capture force of a laser beam; (b) disposing the insulating granular spacer captured with the optical forceps apparatus on one of a pair of display device substrates at a predetermined position; and (c) stacking the pair of display device substrates via the insulating granular spacer. A display device is provided which can set the distance between a pair of display device substrates uniform and suppress the display quality from being lowered.Type: ApplicationFiled: December 9, 2002Publication date: June 26, 2003Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Yasufumi Kanayama, Kiyoshi Ozaki, Makoto Morishige, Takeshi Umegaki
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Patent number: 6476881Abstract: To provide a liquid crystal display device which allows disconnection defects caused in the manufacturing process to be readily repaired with a higher success rate than conventional cases so that the device can be modified into a non-defective device, and a defect repairing method therefor. In a liquid crystal display device having a lead-out portion provided at a lowermost layer bus line 1 formed on a transparent insulating substrate 6, and a pixel electrode layer 3 formed on the lead-out portion through insulating layers 2, 4, an independent intermediate conductive layer 5 is formed between the lead-out portion and said pixel electrode layer 3.Type: GrantFiled: February 6, 2001Date of Patent: November 5, 2002Assignee: Fujitsu LimitedInventors: Kiyoshi Ozaki, Kouji Tsukao, Satoru Kawai
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Patent number: 6469769Abstract: It is intended to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost by decreasing the number of masks. A gate insulating film, a semiconductor film, and a silicon nitride film are laid on a substrate on which a gate bus line is formed, back exposure is performed by using the gate bus line as a mask, and the silicon nitride film is then patterned, whereby a channel protective film is formed along the gate bus line. Two device isolation holes are formed over the gate bus line at two locations that are on both sides of a source electrode and a drain electrode and that are separated from each other in the extending direction of the gate bus line.Type: GrantFiled: June 7, 2001Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventor: Kiyoshi Ozaki
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Publication number: 20020131010Abstract: The present invention relates to a liquid crystal display device and a defect repairing method for the same, and has an object to provide a liquid crystal display device in which a disconnection defect occurring in a storage capacitor bus line can be repaired without producing a new point defect, and a defect repairing method for the same.Type: ApplicationFiled: September 19, 2001Publication date: September 19, 2002Applicant: FUJITSU LIMITEDInventors: Kiyoshi Ozaki, Tsuyoshi Kamada, Kouji Tsukao
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Publication number: 20010040649Abstract: It is intended to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost by decreasing the number of masks. A gate insulating film, a semiconductor film, and a silicon nitride film are laid on a substrate on which a gate bus line is formed, back exposure is performed by using the gate bus line as a mask, and the silicon nitride film is then patterned, whereby a channel protective film is formed along the gate bus line. Two device isolation holes are formed over the gate bus line at two locations that are on both sides of a source electrode and a drain electrode and that are separated from each other in the extending direction of the gate bus line.Type: ApplicationFiled: June 7, 2001Publication date: November 15, 2001Applicant: FUJITSU LIMITEDInventor: Kiyoshi Ozaki
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Publication number: 20010028417Abstract: To provide a liquid crystal display device which allows disconnection defects caused in the manufacturing process to be readily repaired with a higher success rate than conventional cases so that the device can be modified into a non-defective device, and a defect repairing method therefor. In a liquid crystal display device having a lead-out portion provided at a lowermost layer bus line 1 formed on a transparent insulating substrate 6, and a pixel electrode layer 3 formed on the lead-out portion through insulating layers 2, 4, an independent intermediate conductive layer 5 is formed between the lead-out portion and said pixel electrode layer 3.Type: ApplicationFiled: February 6, 2001Publication date: October 11, 2001Applicant: FUJITSU LIMITEDInventors: Kiyoshi Ozaki, Kouji Tsukao, Satoru Kawai
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Publication number: 20010028418Abstract: There is provided a fault repairing method for a liquid crystal display device capable of repairing simply a disconnected portion when a disconnection fault occurs in a display panel. For example, it is on the assumption that the disconnected portion is present in a data bus line. Disconnection repairing contact holes that have a width larger than that of the data bus line are formed in a protection insulating film on the data bus line on both sides of the disconnected portion respectively. Then, a laser CVD film (metal film) for covering inner surfaces of the disconnection repairing contact holes is formed by the laser CVD method, and then respective laser CVD films are connected electrically.Type: ApplicationFiled: March 28, 2001Publication date: October 11, 2001Applicant: FUJITSU LIMITEDInventors: Kiyoshi Ozaki, Kenichi Nagaoka, Kunio Matsubara, Yoji Nagase
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Publication number: 20010022366Abstract: A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film.Type: ApplicationFiled: May 21, 2001Publication date: September 20, 2001Applicant: Fujitsu LimitedInventors: Satoru Kawai, Kiyoshi Ozaki, Jun Inoue, Yoshio Dejima, Kenji Okamoto
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Patent number: 6259494Abstract: A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film.Type: GrantFiled: January 22, 1998Date of Patent: July 10, 2001Assignee: Fujitsu LimitedInventors: Satoru Kawai, Kiyoshi Ozaki, Jun Inoue, Yoshio Dejima, Kenji Okamoto
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Patent number: 6184947Abstract: A thin film transistor matrix including: a plurality of thin film transistors disposed in a matrix shape on a transparent insulating substrate, each thin film transistor having a gate electrode, a source electrode and a drain electrode; a pixel electrode formed on the transparent insulating substrate and connected to the source electrode of each of the plurality of thin film transistors; a plurality of gate bus lines connected to the gate electrode, disposed as a whole along a row direction on the transparent insulating substrate, and including a first lamination of a first metal layer and an underlying first semiconductor layer; and a plurality of drain bus lines connected to the drain electrode, disposed as a whole along a column direction on the transparent insulating substrate, and including a second lamination of a second metal layer and an underlying second semiconductor layer.Type: GrantFiled: July 6, 1999Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Kiyoshi Ozaki, Makoto Igarashi
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Patent number: 4820549Abstract: A photo-curable resist resin composition for electroless plating comprising an epoxy resin having a viscosity of at least 150 poises at 25.degree. C., and at least two glycidyl ether groups in one molecule, the glycidyl ether groups being directly bonded to the aromatic ring as Component A, an oxirane ring-containing compound having a boiling point of at least 140.degree. C. and a molecular weight of not more than 500 as Component B, and a photo-sensitive aromatic onium salt as Component C, wherein the Component A is in an amount of 90 to 40 parts by weight per total 100 parts by weight of the Components A and B, and the Component C is in an amount of 0.Type: GrantFiled: May 19, 1987Date of Patent: April 11, 1989Assignee: Hitachi, Ltd.Inventors: Kiyoshi Ozaki, Atsushi Mori, Hideo Tsuda, Mineo Kawamoto, Kanji Murakami, Motoyo Wajima
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Patent number: 4464459Abstract: A method of forming a pattern of metal elements arranged with very small gaps therebetween on a substrate in magnetic bubble memory devices, semiconductor devices, and the like. In this method, first, a pattern forming layer having metal portions adapted for forming pattern elements and insulating portions for providing the gaps is formed on the substrate, and thereafter the pattern forming layer is processed by using a photolithograhic technique to form the pattern. By using this method, it is possible to form a permalloy propagation pattern with gaps of a size smaller than 1 .mu.m in a magnetic bubble memory device, for example, by using conventional photolithograhic techniques.Type: GrantFiled: June 25, 1982Date of Patent: August 7, 1984Assignee: Fujitsu LimitedInventors: Teiji Majima, Kiyoshi Ozaki