Abstract: A semiconductor memory device which may be formed in a parallel array for high density integration is disclosed. The memory device includes a multigate memory transistor formed in a first semiconductor region of one conductivity type in a substrate of the opposite conductivity type. The memory transistor is formed with source and drain regions of opposite conductivity type and a gate insulating layer formed on the surface between the source and drain regions. A plurality of gate electrodes are formed on the gate insulating layer and laterally separated from each other. A plurality of opposite conductivity type regions are formed in the first semiconductor region under the respective intervals between adjacent gate electrodes.