Patents by Inventor Kiyoshi Takaoki

Kiyoshi Takaoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4792534
    Abstract: A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type semiconductor layer. A first mask layer, such as an aluminum layer having an etching rate different from that of the insulating films, is formed on the insulating films. A second mask layer having an etching rate different from that of the first mask layer, is formed on the first mask layer. The second mask layer is patterned. A coating film having an etching rate different from that of the first insulating film, is formed on the resultant structure. The coating film is etched to be left on a side wall of the patterned second mask layer. The first mask layer is patterned, using the residual coating film and the patterned second mask layer as masks, and a pattern finer than that of the resist is formed in the first mask layer.
    Type: Grant
    Filed: December 15, 1986
    Date of Patent: December 20, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Tsuji, Tiharu Kato, Kiyoshi Takaoki
  • Patent number: 4146413
    Abstract: A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.
    Type: Grant
    Filed: November 2, 1976
    Date of Patent: March 27, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Toshio Yonezawa, Toshio Mitsuno, Kiyoshi Takaoki, Takashi Ajima
  • Patent number: 4123564
    Abstract: A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming a first insulation film and selectively forming a second insulation film on predetermined portions of the first insulation film by the use of a polycrystalline silicon film as the mask.
    Type: Grant
    Filed: December 2, 1976
    Date of Patent: October 31, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Takashi Ajima, Kiyoshi Takaoki, Toshio Yonezawa