Patents by Inventor Kiyoshi Uchiyama

Kiyoshi Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030080325
    Abstract: A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Applicant: Symetrix Corporation and Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Publication number: 20030034509
    Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal.
    Type: Application
    Filed: September 30, 2002
    Publication date: February 20, 2003
    Applicant: Matsushita Electric Industrial Co, Ltd.
    Inventor: Kiyoshi Uchiyama
  • Publication number: 20030006440
    Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 9, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Uchiyama
  • Patent number: 6489645
    Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: December 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Uchiyama
  • Publication number: 20020110934
    Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.
    Type: Application
    Filed: February 12, 2001
    Publication date: August 15, 2002
    Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Keisuke Tanaka
  • Patent number: 6396095
    Abstract: Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: May 28, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Shimada, Koji Arita, Kiyoshi Uchiyama
  • Publication number: 20020036314
    Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.
    Type: Application
    Filed: September 20, 2001
    Publication date: March 28, 2002
    Inventors: Kiyoshi Uchiyama, Yasuhiro Shimada, Koji Arita, Tatsuo Otsuki
  • Patent number: 6351004
    Abstract: A tunneling transistor is provided as an effective means for miniaturization of a semiconductor integrated circuit having nonvolatile memory. An insulating layer is disposed on a silicon substrate. A source and a drain are disposed on the insulating layer, with an insulator of a few nanometers in thickness that provides a tunnel barrier being interposed between the source and the drain. A ferroelectric layer that exhibits spontaneous polarization is disposed directly above a region of the source that is adjacent to the insulator. With this construction, when the ferroelectric layer is polarized in a predetermined direction, at least a portion of the region of the source adjacent to the insulator forms a depletion region, with it being possible to vary the amount of current tunneling through the insulator depending on whether the ferroelectric layer is polarized or not.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: February 26, 2002
    Assignee: Matsushita Electric Ind. Co., Ltd.
    Inventors: Yasuhiro Shimada, Shinichiro Hayashi, Kiyoshi Uchiyama, Keisuke Tanaka
  • Patent number: 6326315
    Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: December 4, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Kiyoshi Uchiyama, Koji Arita, Narayan Solayappan, Carlos A. Paz de Araujo
  • Publication number: 20010019497
    Abstract: Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data “1” while the up or almost zero remnant polarization may represent data “0”, for example. By regarding the almost zero remnant polarization state as representing data “0”, a read current value becomes substantially constant in the data “0” state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data “1”) is induced in advance, then the read accuracy further improves.
    Type: Application
    Filed: February 14, 2001
    Publication date: September 6, 2001
    Inventors: Yasuhiro Shimada, Koji Arita, Kiyoshi Uchiyama
  • Patent number: 5222074
    Abstract: A thermal decomposition cell for producing a molecular beam from a material gas, includes: a crucible maintained at a given temperature necessary for thermal decomposition of the material gas which is effused in the crucible in a given direction; and a thermal decomposition baffle provided in the crucible and heated to a given temperature necessary for thermal decomposition of the material gas for producing the molecular beam by thermal-decomposing of the material gas such that the material gas is baffled in substantially all directions, the thermal decomposition baffle being made of a given metal to cause the thermal decomposition of the material gas. The thermal decomposition baffle may comprise a fiber or a cloth made of the metal loaded in the crucible.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: June 22, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Tomoko Suzuki, Tatsuo Yokotsuka, Akira Takamori, Masato Nakajima
  • Patent number: 5194400
    Abstract: A method for fabricating an AlGaInP-based visible light laser device by molecular beam epitaxy is described. In this method, a upper clad layer of (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P wherein x and y are, respectively, in the ranges of from 0.5 to 1 and from 0.47 to 0.53 is covered with a protective layer serving also as an etching prevenive layer so that a grooved-type structure using the (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P clad layer can be fabricated without involving degradation of the clad layer by contamination with oxygen, nitrogen and the like.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: March 16, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Takamori, Ken Idota, Kiyoshi Uchiyama, Masato Nakajima
  • Patent number: 4998859
    Abstract: A transferring apparatus comprises a vacuum chamber, a carrier member disposed inside a pipe which communicates with the vacuum chamber, magnetic means installed in a support structure which is moved by a driving means. The carrier member is floated and pulled in its axial direction by magnetic force produced by the magnetic means, whereby an object placed on the tip of a manipulator arm which is connected to the carrier member is transferred in the vacuum chamber. Since the carrier member is floated inside the pipe and moved in its axial direction without contact to the pipe or any other parts, there are no portions inside the pipe which relatively move in contact with each other, and thus fine particles are not generated inside the pipe. This effectively eliminates adhesion of fine particles to objects such as semiconductor devices being transferred in a vacuum chamber.
    Type: Grant
    Filed: September 19, 1988
    Date of Patent: March 12, 1991
    Assignee: Seiko Seiki Kabushik Kaisha
    Inventors: Zinichiro Oshima, Kiyoshi Uchiyama, Ikuo Nanno