Patents by Inventor Kiyoshi Yoneda
Kiyoshi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10736199Abstract: This information processing method is executed by an electric light bulb light source apparatus, which includes a lighting unit, and a functional unit, the information processing method including: selecting, from any of a parent mode and a child mode, an operation mode for cooperative control with a different electric light bulb light source apparatus with respect to the functional unit, and setting the selected operation mode. In a case where the parent mode is set, the lighting unit is caused to execute a first lighting operation for the parent mode in response to a predetermined lighting control signal relating to an operation of the lighting unit, and a cooperative control signal for causing a second lighting operation for the child mode to be executed is transmitted to the different electric light bulb light source apparatus set to the child mode, the second lighting operation for the child mode being different from the first lighting operation.Type: GrantFiled: November 15, 2016Date of Patent: August 4, 2020Assignee: SONY CORPORATIONInventors: Naoki Yotsumoto, Takashi Sato, Kiyoshi Yoneda
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Publication number: 20180324932Abstract: This information processing method is executed by an electric light bulb light source apparatus, which includes a lighting unit, and a functional unit, the information processing method including: selecting, from any of a parent mode and a child mode, an operation mode for cooperative control with a different electric light bulb light source apparatus with respect to the functional unit, and setting the selected operation mode. In a case where the parent mode is set, the lighting unit is caused to execute a first lighting operation for the parent mode in response to a predetermined lighting control signal relating to an operation of the lighting unit, and a cooperative control signal for causing a second lighting operation for the child mode to be executed is transmitted to the different electric light bulb light source apparatus set to the child mode, the second lighting operation for the child mode being different from the first lighting operation.Type: ApplicationFiled: November 15, 2016Publication date: November 8, 2018Inventors: NAOKI YOTSUMOTO, TAKASHI SATO, KIYOSHI YONEDA
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Patent number: 9723700Abstract: There is provided an illumination apparatus including an illumination unit, a reception unit, and a control unit configured to control illumination of the illumination unit in accordance with a default illumination pattern. When the reception unit receives an illumination pattern, the control unit performs illumination control different from the illumination according to the default illumination pattern.Type: GrantFiled: February 26, 2016Date of Patent: August 1, 2017Assignee: SONY CORPORATIONInventors: Yoichiro Sako, Kazuhiro Watanabe, Kazuyuki Sakoda, Hiroshi Okada, Hirofumi Yuchi, Kohei Asada, Takashi Sato, Yutaka Fukuyama, Kiyoshi Yoneda, Kouji Miyata
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Publication number: 20160183349Abstract: There is provided an illumination apparatus including an illumination unit, a reception unit, and a control unit configured to control illumination of the illumination unit in accordance with a default illumination pattern. When the reception unit receives an illumination pattern, the control unit performs illumination control different from the illumination according to the default illumination pattern.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Inventors: Yoichiro SAKO, Kazuhiro WATANABE, Kazuyuki SAKODA, Hiroshi OKADA, Hirofumi YUCHI, Kohei ASADA, Takashi SATO, Yutaka FUKUYAMA, Kiyoshi YONEDA, Kouji MIYATA
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Patent number: 9307617Abstract: There is provided an illumination apparatus including an illumination unit, a reception unit, and a control unit configured to control illumination of the illumination unit in accordance with a default illumination pattern. When the reception unit receives an illumination pattern, the control unit performs illumination control different from the illumination according to the default illumination pattern.Type: GrantFiled: August 20, 2013Date of Patent: April 5, 2016Assignee: SONY CORPORATIONInventors: Yoichiro Sako, Kazuhiro Watanabe, Kazuyuki Sakoda, Hiroshi Okada, Hirofumi Yuchi, Kohei Asada, Takashi Sato, Yutaka Fukuyama, Kiyoshi Yoneda, Kouji Miyata
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Publication number: 20140070729Abstract: There is provided an illumination apparatus including an illumination unit, a reception unit, and a control unit configured to control illumination of the illumination unit in accordance with a default illumination pattern. When the reception unit receives an illumination pattern, the control unit performs illumination control different from the illumination according to the default illumination pattern.Type: ApplicationFiled: August 20, 2013Publication date: March 13, 2014Applicant: SONY CORPORATIONInventors: YOICHIRO SAKO, KAZUHIRO WATANABE, KAZUYUKI SAKODA, HIROSHI OKADA, HIROFUMI YUCHI, KOHEI ASADA, TAKASHI SATO, YUTAKA FUKUYAMA, KIYOSHI YONEDA, KOUJI MIYATA
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Patent number: 7439114Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: GrantFiled: August 18, 2005Date of Patent: October 21, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Patent number: 7199514Abstract: An organic EL element with an emissive layer and a second electrode layer is formed on a device glass substrate in an organic EL display device. The second electrode layer covers the emissive layer. An anti-reflection layer for preventing the reflection of light by the second electrode layer is formed on the device glass substrate except the region where the emissive layer is formed. Since this layer prevents the reflection of light by the second electrode layer, only the light from the emissive layer radiates outwards through the device glass substrate, improving the contrast of the organic EL display device.Type: GrantFiled: May 23, 2003Date of Patent: April 3, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Kiyoshi Yoneda
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Patent number: 7166959Abstract: A display device includes a plurality of pixels and realizes a color display using emitted light of at least two wavelengths. Each pixel has a microresonator structure formed between a lower reflective film formed on a side near a substrate and an upper reflective film formed above the lower reflective film with an organic light emitting element layer therebetween. A conductive resonator spacer layer is provided between the lower reflective film and the organic light emitting element layer. Light obtained in the organic light emitting element layer is intensified by the microresonator structure in which the optical length is adjusted by the conductive resonator spacer layer and is emitted to the outside.Type: GrantFiled: December 22, 2004Date of Patent: January 23, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Koji Suzuki, Ryuji Nishikawa, Kiyoshi Yoneda
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Patent number: 7163850Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.Type: GrantFiled: September 20, 2004Date of Patent: January 16, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
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Patent number: 7098474Abstract: A hole injecting electrode composed of ITO is formed on a glass substrate. On the hole injecting electrode, a hole injecting layer composed of CuPc (copper phthalocyanine), a plasma thin film of CFx formed by plasma CVD, a hole transporting layer of NPB, and a light emitting layer are formed in the order. On the light emitting layer, an electron transporting layer is formed, and an electron injecting electrode is formed thereon.Type: GrantFiled: September 24, 2003Date of Patent: August 29, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroshi Kanno, Kiyoshi Yoneda, Kazuki Nishimura, Yuji Hamada
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Patent number: 7095389Abstract: The display device of this invention, in which the retaining circuit for retaining the image signal is provided for each of the pixel elements, is capable of operating under two operation modes, a normal operation mode and a memory mode. Since the placement of the retaining circuit 110, which requires relatively large area, is confined to the area for the pixel element electrode 17 not in between the neighboring pixel element electrodes 17, the required area for one pixel element is minimized, resulting in the size reduction of the liquid crystal display device. By placing at least a portion of the retaining circuit in the area of the pixel element electrode 17 of the neighboring pixel element, the detour of the wiring can be omitted, resulting in the efficient use of the space. By this, the area required for the retaining circuit is minimized, directly resulting in the reduction of the size of the liquid crystal display device.Type: GrantFiled: September 17, 2001Date of Patent: August 22, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Hisao Uehara, Kiyoshi Yoneda, Yasushi Miyajima, Ryoichi Yokoyama
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Patent number: 7084052Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.Type: GrantFiled: August 13, 2004Date of Patent: August 1, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda
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Patent number: 7081875Abstract: In the display device having the retaining circuit for holding the digital image data at the pixel element, the power voltage supplied to the retaining circuit 110 is set up to be at the minimum level for the retaining circuit to hold the data during the data writing period, but the voltage supplied to the retaining circuit is raised by the voltage booster 95 upon the completion of the data writing. The retaining circuit 110 takes in the digital image signal fed from the drain signal line 61 in response to the signal fed from the gate signal line 51 and holds the digital image signal. Then, the display is carried out according to the signal held by the retaining circuit 110. By this, the erroneous writing of the data to the retaining circuit is prevented. The reduction of the electric power consumption and the high density integration of the pixel elements are also possible.Type: GrantFiled: September 17, 2001Date of Patent: July 25, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Ryoichi Yokoyama, Kiyoshi Yoneda
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Patent number: 7061017Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: GrantFiled: November 14, 2003Date of Patent: June 13, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Patent number: 7045818Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.Type: GrantFiled: April 5, 2004Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Yushi Jinno, Shiro Nakanishi, Kyoko Hirai, Tsutomu Yamada, Yoshihiro Morimoto, Kiyoshi Yoneda
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Patent number: 7019458Abstract: In an organic EL panel having a device glass substrate provided with an organic EL element on a surface thereof, a sealing glass substrate attached to the device glass substrate and a desiccant layer formed on a surface of the sealing glass substrate, spacers are disposed between a cathode of the organic EL element and the desiccant layer. A heat-conductive layer can be formed on a surface of the sealing glass substrate including a pocket portion. The heat-conductive layer can be formed by vapor depositing or sputtering a metal layer such as a Cr layer or an Al layer. This inhibits damaging the organic EL element and increases a heat dissipating ability, thereby inhibiting deterioration of a device property caused by temperature rise.Type: GrantFiled: May 23, 2003Date of Patent: March 28, 2006Assignee: Sanyo Electric Co., Ltd.Inventor: Kiyoshi Yoneda
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Patent number: 6995048Abstract: A first contact hole is formed penetrating a gate insulating film, on which a gate electrode is formed and simultaneously a first contact is formed in the first contact hole. A second contact hole penetrating an interlayer insulating film is formed, and a second contact is formed in the second contact hole. A third contact hole is formed penetrating a planarization film, and an electrode is formed in the third contact hole. By using a plurality of contact holes for electrically connecting the electrode and a semiconductor film, the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.Type: GrantFiled: May 16, 2002Date of Patent: February 7, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Kiyoshi Yoneda, Tsutomu Yamada, Shinji Yuda, Koji Suzuki
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Publication number: 20050287825Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: ApplicationFiled: August 18, 2005Publication date: December 29, 2005Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi kuwahara
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Patent number: 6960890Abstract: The invention prevents an uneven display on an organic EL display panel by reducing characteristic variation of a driving transistor among pixels. A gate signal line for supplying a gate signal and a drain signal line for supplying a display signal are crossing each other. Four split driving TFTs of P-channel type are provided in a pixel, and drains of the driving TFTs are connected with anodes of split organic EL elements, respectively. A common gate of the driving TFTs is connected with a pixel selecting TFT.Type: GrantFiled: March 2, 2004Date of Patent: November 1, 2005Assignee: Sanyo Electric Co., Ltd.Inventor: Kiyoshi Yoneda