Patents by Inventor Kiyoshi Yoneda

Kiyoshi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5635763
    Abstract: A semiconductor device is disclosed, which includes an insulating layer and an interconnection layer having a conductive layer provided over the insulating layer. The interconnection layer is patterned by photolithography. The device further includes a cap-metal layer, which is deposited on the conductive layer and suppresses reflection of light beams at the time of patterning the interconnection layer. The cap-metal layer has any one of the following structures: a double-layered structure having a titanium nitride layer and a titanium layer located between the titanium nitride layer and the conductive layer; a double-layered structure having a titanium nitride layer and an aluminum-titanium alloy layer located between the titanium nitride layer and the conductive layer; and a single-layered structure consisting essentially of an aluminum-titanium alloy. These design ensure accurate interconnection patterning in the photolithography, and provide improved EM and SM immunities of the interconnection.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: June 3, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Kazutoshi Tsujimura, Shinichi Tanimoto, Yasuhiko Yamashita, Kiyoshi Yoneda, Yoshikazu Ibara
  • Patent number: 5444653
    Abstract: Disclosed is a semiconductor memory device which has stack type memory cells each comprising one MIS transistor and one MIS capacitor. A first conductive film having a predetermined thickness is arranged to overlay a memory node contact of a memory cell which corresponds to a source or drain region of the MIS transistor. A second conductive film is formed on the surface of the first conductive film to have a predetermined thickness and come in contact with the source or drain region by means of a memory node contact hole formed inside the memory node contact. The first and second conductive films form a capacitor electrode of the MIS capacitor.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: August 22, 1995
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideharu Nagasawa, Kazunari Honma, Yasuhiro Takeda, Kiyoshi Yoneda
  • Patent number: 4935092
    Abstract: The invention relates to a method of growing a single crystal CaF.sub.2 film on a single crystal Si substrate having a principal plane of (100). According to the invention, the substrate temperature is first set at 550.degree.-600.degree. C. to grow a first CaF.sub.2 film (first stage) and the substrate temperature is then raised to 750.degree. C. or higher to grow a second CaF.sub.2 film on the first CaF.sub.2 film (second stage), thus the growth of the CaF.sub.2 films is performed separately in two stages. Since, in the second stage, the growth of CaF.sub.2 film is possible even at higher substrate temperature, the method of growing according to the invention makes it possible to grow a single crystal CaF.sub.2 film with flat surface morphology and excellent crystal quality.
    Type: Grant
    Filed: October 6, 1988
    Date of Patent: June 19, 1990
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshihiro Morimoto, Kiyoshi Yoneda, Shoji Sudo, Shoichiro Matsumoto
  • Patent number: 4906594
    Abstract: This invention relates to a surface smoothing method for smoothing the surface of a semiconductor film and insulating film, etc, and a method of forming and SOI substrate by using this surface smoothing method. In this surface smoothing method, the surface of a semiconductor film or an insulating film formed on a substrate is irradiated with an ion beam at an incident angle of about 85.degree. or more, to the normal direction of the surface, while revolving the substrate, whereby the surface is smoothed easily without any contamination thereof or physical deformation of the surface layer.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: March 6, 1990
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kiyoshi Yoneda, Kazunobu Mameno, Keita Kawahara, Yasunori Inoue
  • Patent number: 4833100
    Abstract: The present invention relates to a method for producing a semiconductor thin film, in which a single crystalline silicon film is grown on an insulative single crystalline substrate, such as a single crystalline sapphire substrate, by the molecular beam epitaxy method. Silicon molecular beams are irradiated onto the substrate under the conditions wherein a substrate temperature is kept at 700.degree. to 900.degree. C. and an intensity of the molecular beams is kept within a range from 1.times.10.sup.12 atoms/cm.sup.2 .multidot.sec to 1.times.10.sup.13 atoms/cm.sup.2 .multidot.sec to clean a surface of the substrate and then the intensity of the molecular beams is increased to form the single crystalline silicon film. Thus, the substrate can be cleaned without being defected.
    Type: Grant
    Filed: December 8, 1986
    Date of Patent: May 23, 1989
    Assignee: Kozo Iizuka, Director-General of Agency of Industrial Science and Technology
    Inventors: Hiroshi Hanafusa, Kiyoshi Yoneda, Hidenori Ogata
  • Patent number: 4831948
    Abstract: A tufting machine is provided with a needle block movable up and down, needle carriers mounted on the needle block, the carriers carrying needles aligned crosswisely of the machine, wherein the needles are individually driven to insert into a backing fabric by means of actuators operatively connected to each of them and a needle selector for selecting the needles by controlling the operation of the actuators.
    Type: Grant
    Filed: May 6, 1988
    Date of Patent: May 23, 1989
    Assignees: Suminoe Orimono Kabushiki Kaisha, Kabushiki Kaisha Yoneda Tekkoh
    Inventors: Sigeki Itoh, Kiyoshi Yoneda
  • Patent number: 4536842
    Abstract: An elevator passenger traffic measuring system distributes passengers whose destination floors cannot be determined to each of origin-destination floor pairs in accordance with an elevator car position, an incoming passenger number and an outgoing passenger number at each floor, and registered car calls, using probability weights for the origin-destination floor pairs which are determined by previous traffic measurements. The system then estimates the number of passengers for each of the origin-destination floor pairs in accordance with the distributed passengers, and the passengers who moved the corresponding one of the origin-destination floor pairs.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: August 20, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kiyoshi Yoneda, Hiroshi Takeuchi, Tetsuo Yamatani, Toyoto Hijiya, Hideo Takeda, Koji Shibuya, Kiichiro Tanaka