Abstract: Provided is a battery protection circuit and a battery device which may be manufactured at lower cost. Before all terminals of a battery protection circuit are each connected to batteries, even when a logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by P-wells due to a connection order in which the batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the P-wells. For this reason, a charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order.

Abstract: In order to provide an overheat protection circuit having a small mounting area, the overheat protection circuit includes: a resistor bridge circuit which includes: a plurality of resistors each having a temperature coefficient; an input terminal; and an output terminal; and a comparator circuit connected to the output terminal and the input terminal of the resistor bridge circuit. Parts are each provided in the vicinity of one of the plurality of resistors each having the temperature coefficient, and the comparator circuit outputs an overheat detection signal when a temperature of one of the parts is equal to or higher than an overheat detection temperature. With this structure, a large number of parts can be protected from overheating by a minimum number of overheat protection circuits. Therefore, a circuit scale becomes smaller, and hence a cost for overheat protection becomes lower.

Abstract: Provided is a power supply switching circuit capable of efficiently supplying a desired voltage among a plurality of voltages to a load. In the case of a P-type semiconductor substrate, N-type MOS transistors are provided between a load and an AC adapter and between the load and a battery, and hence no parasitic diode exists between the load and the AC adapter or the battery, resulting in no current path due to the parasitic diode. Thus, when the AC adapter and the battery are connected to the power supply switching circuit, the N-type MOS transistor is turned off, whereby the current path between the battery and the load is cut off completely and the N-type MOS transistor is turned on. Accordingly, the battery cannot supply a voltage to the load while only the AC adapter can supply a voltage to the load.

Abstract: A charge and discharge control circuit which accommodates pulsed charge and pulsed discharge and can control charge and discharge of a secondary battery with safety, and a rechargeable power supply device having the same built therein are provided. The charge and discharge control circuit includes a delay time switching circuit for shortening a delay time of overcharge detection after charge inhibition is canceled. When overcharge is detected after the charge inhibition is canceled, the charge is inhibited in a delay time which is shorter than a normal delay time of the overcharge detection.

Abstract: Provided is a battery state monitoring circuit which is capable of preventing a discharge leak current from a battery so as to eliminate a load conventionally imposed on a user, including: a battery state detector circuit that detects a state of the battery based on a voltage of the battery; a transmitting terminal that transmits battery state information indicative of the state of the battery to an outside; a receiving terminal that receives battery state information of another battery from the outside; a transistor that is used for transmitting the battery state information, and has any one of two terminals except for a control terminal connected to the transmitting terminal; and a diode that is connected in a direction opposite to a direction of a parasitic diode disposed between the two terminals of the transistor, the diode being disposed between the transmitting terminal and one terminal of the transistor.

Abstract: Provided are a switched capacitor amplifier capable of removing an influence of an offset voltage and a 1/f noise using a simple circuit, and a method of operating the same.

Abstract: A voltage regulator according to the present invention is operated stably. Regardless of a condition of a load (25), a variation in drain voltage of a PMOS transistor (34) is made equal to a variation in output voltage (Vout) at an output terminal of the voltage regulator. Then, a variation in voltage which is equal to the variation in output voltage (Vout) at the output terminal which is caused by a change of the condition of the load (25) is fed back to an error amplifier (70), so a gain of a signal for phase compensation which is fed back to the error amplifier (70) is determined based on the output voltage (Vout). Therefore, even when the condition of the load (25) changes, the behavior of phase compensation is correct.

Abstract: Provided are a switched capacitor amplifier capable of removing an influence of an offset voltage and a 1/f noise using a simple circuit, and a method of operating the same.

Abstract: A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

Abstract: A variable delay circuit comprising a positive logic variable delay circuit for delaying an edge of a signal input through an input terminal and a negative logic variable delay circuit for delaying an edge of a signal input through an input terminal, in which only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit.

Abstract: A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

Abstract: A variable delay circuit has a positive logic variable delay circuit which delays an edge of a signal which is input through an input terminal and a negative logic variable delay circuit which delays an edge of the signal input through an input terminal. Only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit in an extracting circuit of the variable delay circuit.

Abstract: A vapor deposition device for fabricating a compound semiconductor has many organometallic gas supply systems, each of which for synthesizing and supplying more than one organometallic gas, a first group of valves connected to the organometallic gas supply systems, and the first group of valves for selecting a specific system from among the organometallic gas supply systems by opening and closing the relevant valve group, an organometallic gas supply line connected to the first valve group, a second group of valves connected to the first group of valves for selecting the next organometallic gas supply system to be used among the organometallic gas supply systems by opening and closing the relevant valve group, a vent line connected to the second valve group, a reaction furnace connected to the organometallic gas supply means for continuously propagating different types of thin-films by means of organometallic gases supplied from the organometallic gas supply line, a microcomputer system for controlling the op

Abstract: A process for coating a substrate surface with a diamond-like carbon film, in which a starting material gas comprising a hydrocarbon compound is introduced into a Hall accelerator ion source with an inner pressure thereof reduced to 1.times.10.sup.-5 to 1.times.10.sup.-1 Torr, an ion beam in which 80% or more of the ion beams formed have an impinging energy in the range of 100 to 1500 eV is formed in the ion source, and irradiated onto a substrate comprising various kinds of materials in a vacuum chamber, to thereby coat the substrate surface with a diamond-like carbon film with a strong adhesion to an extent such that is can with stand practical application.

Abstract: A semiconductor treatment apparatus has a gas-phase decomposing device for decomposing a gas-phase on a surface of a semiconductor substrate, a substrate supporting device for supporting the substrate, and a substrate transfer device for transferring the substrate between the gas-phase decomposing device and the substrate supporting device. The apparatus further has a liquid-drop applicator for applying a liquid-drop on the surface of the substrate supported by the substrate supporting device, with the liquid-drop being brought into contact with the surface of the substrate, and a liquid-drop preserving device for preserving the liquid-drop that has been applied to the surface of the substrate.

Abstract: A vapor growth apparatus has a susceptor which rotates in a water cooled reaction tube with holding semiconductor susbstrates thereon. A heater is provided in order to heat the susceptor and to maintain a predetermined temperature. This heater is comprised of an inner heater, which heats the inner part of the susceptor, and a peripheral heater, which heats the peripheral part of the susceptor. The peripheral heater is made thicker than the inner heater. In addition, these inner and peripheral heaters are connected in parallel with each other. So, the peripheral heater can generate more heat than the inner heater so as to compensate the temperature decrease in the peripheral part of the susceptor, without loosing the mechanical strength of the whole heater.

Abstract: There is provided a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber.

Abstract: A semiconductor substrate etching apparatus for etching a tapered outer circumferential surface of a semiconductor substrate. A semiconductor substrate supply unit, an X-Y stage unit, an etchant applying unit, a cleaning unit, a baking unit, and a semiconductor substrate recovering unit are arranged in a horizontal plane in the described order. Semiconductor substrates are sequentially transferred by a transfer mechanism from the semiconductor substrate supply unit to the semiconductor substrate recovering unit in the described order. A control unit controls the transfer mechanism to perform the transferring of the semiconductor substrate, and controls the X-Y stage unit in response to a position detection signal, outputted from a position detector, for positioning the semiconductor substrate on the X-Y stage unit.

Abstract: There is provided a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber.

Abstract: A semiconductor substrate etching apparatus is disclosed. In this apparatus, a semiconductor substrate is mounted on the upper surface of a first vacuum chuck, an etching solution is supplied to a groove of a roller of a semiconductor substrate end surface etching mechanism, which covers the end surface of the semiconductor substrate, and the first vacuum chuck and the roller are rotated in the opposite directions. The end surface of the semiconductor substrate is brought into contact with the etching solution. The etching solution is then transferred onto the end surface of the substrate, thus performing etching of the end surface.