Abstract: According to an embodiment, an encoder system includes an encoder and an interface. The encoder detects the position and speed of a motor, and generates A-, B- and Z-phase signals. The interface includes an AB waveform recognition circuitry to recognize a waveform of an AB phase, a Z waveform recognition circuitry to recognize a period of an enable state of a Z phase, a starting point storage device to store a value of the AB phase when the Z phase changes and stores an AB-phase change pattern, a starting point recognition circuitry to generate an interrupt signal, and a rotation angle counter to start a new count of the rotation angle of the motor.

Abstract: According to one embodiment, a supervisory circuit includes a trigger determination circuit and a trigger table. The trigger determination circuit receives signal processing signals outputted from a plurality of signal processing circuits as trigger signals, determines whether processing operations by the signal processing circuits are executed in a predetermined order, and outputs an interrupt signal when detecting a trigger signal out of setting. The trigger table is provided with trigger-specific tables corresponding to the respective signal processing circuits, reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and outputs a table read signal to the trigger determination circuit.

Abstract: According to an embodiment, an encoder system includes an encoder and an interface. The encoder detects the position and speed of a motor, and generates A-, B- and Z-phase signals. The interface includes an AB waveform recognition circuitry to recognize a waveform of an AB phase, a Z waveform recognition circuitry to recognize a period of an enable state of a Z phase, a starting point storage device to store a value of the AB phase when the Z phase changes and stores an AB-phase change pattern, a starting point recognition circuitry to generate an interrupt signal, and a rotation angle counter to start a new count of the rotation angle of the motor.

Abstract: According to one embodiment, a shared FIFO device includes a write pointer control circuit, a read pointer control circuit, a write pointer selection circuit, a read pointer selection circuit, a selection circuit, and a memory array. The shared FIFO device performs FIFO access through n transfer routes (where n is an integer of 2 or greater).

Abstract: According to one embodiment, a supervisory circuit includes a trigger determination circuit and a trigger table. The trigger determination circuit receives signal processing signals outputted from a plurality of signal processing circuits as trigger signals, determines whether processing operations by the signal processing circuits are executed in a predetermined order, and outputs an interrupt signal when detecting a trigger signal out of setting. The trigger table is provided with trigger-specific tables corresponding to the respective signal processing circuits, reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and outputs a table read signal to the trigger determination circuit.