Abstract: The present invention provides a semiconductor device including an N channel MIS type transistor and a P channel MIS type transistor. The semiconductor device includes a first inter-layer film formed on the NMIS transistor and having a tensile stress, and a second inter-layer film formed on the first inter-layer film and a PMIS transistor and having a compressive stress, and the compressive stress in the second inter-layer film is relaxed on the upper side of the first inter-layer film.

Abstract: The present invention provides a semiconductor device including an N channel MIS type transistor and a P channel MIS type transistor. The semiconductor device includes a first inter-layer film formed on the NMIS transistor and having a tensile stress, and a second inter-layer film formed on the first inter-layer film and a PMIS transistor and having a compressive stress, and the compressive stress in the second inter-layer film is relaxed on the upper side of the first inter-layer film.

Abstract: A method of manufacturing a semiconductor device having an n-type FET and p-type FET, each formed over a semiconductor substrate, calls for (a) forming, over the n-type FET and p-type FET, a first insulating film, for generating a tensile stress in the channel formation region of the n-type FET, to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film, for generating a compressive stress in the channel formation region of the p-type FET, to cover gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.

Abstract: Provided is a method of manufacturing a semiconductor device having an n-type FET and a p-type EFT each formed over a semiconductor substrate, which comprises (a) forming, over the n-type FET and p-type FET, a first insulating film for generating a tensile stress in the channel formation region of the n-type FET so as to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film for generating a compressive stress in the channel formation region of the p-type FET so as to cover the gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.