Abstract: A method of manufacturing a semiconductor device includes: forming a first film containing carbon over a silicon nitride film and a first conductive film; forming a first silicon oxide film surrounding the first film over the silicon nitride film and the first conductive film; removing the first film to form, in the first silicon oxide film, a first opening that exposes at least a part of the silicon nitride film and at least a part of the first conductive film; and forming a second conductive film on and in contact with the first conductive film in the first opening.

Abstract: Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Abstract: Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Abstract: A cable according to the present invention comprising: a connector to be connected to a subject device; a bundle of electric wires for supplying signals and/or power to the connector; and a holding member for holding the connector and the electric wires, the connector and the electric wires being connected inside the holding member, a direction of the connector extending to the outside from the holding member being same with a direction of the electric wire being drawn out to the outside from the holding member.

Abstract: A communication device has a configuration including a data analysis unit 1, a communication monitoring unit 2, and a management information transmission unit 3. The data analysis unit 1 extracts predetermined information from each of a plurality of packets input to the own device, analyzes the predetermined information of the plurality of packets, and generates information relating to a characteristic of each flow of the packets, as flow management information. The communication monitoring unit 2 detects that an abnormality occurs in communication of packets in a communication network to which the own device is connected. When the abnormality detection unit 2 detects the abnormality, the management information transmission unit 3 transmits predetermined information already extracted from a predetermined packet input before the detection of the abnormality, as information for generating the flow management information expected to be generated by the own device, to a standby-system device.

Abstract: A charging connector comprising: a pair of power supply terminals for pinching power supply terminals of a Type-C plug connector complying with the USB connector standard from both sides, and a pair of grounding terminals and for pinching qrounding terminals of the plug connector from both sides; wherein the power supply terminals and the grounding terminals are configured by fork terminals.

Abstract: A charging connector comprising, a pair of power supply terminals for pinching power supply terminals of a Type-C plug connector complying with the USB connector standard from both sides, and a pair of grounding terminals and for pinching grounding terminals of the plug connector from both sides, wherein the power supply terminals and the grounding terminals are configured by fork terminals

Abstract: A cable according to the present invention comprising: a connector to be connected to a subject device; a bundle of electric wires for supplying signals and/or power to the connector; and a holding member for holding the connector and the electric wires, the connector and the electric wires being connected inside the holding member, a direction of the connector extending to the outside from the holding member being same with a direction of the electric wire being drawn out to the outside from the holding member.

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

Abstract: A connector comprises: contacts disposed in a row so as to be mutually parallel; a metal case that comprises one surface which is parallel to the direction of disposition of the contacts and two surfaces which are perpendicular with respect to the direction of disposition of the contacts and sandwich the ends of the disposition of the contacts, and that arranged while kept from contact with the contacts; and a synthetic-resin insulator that is formed so as to encase the contacts and the metal case and that exposes part of the contacts and part of the metal case as external contact points.

Abstract: A communication device has a configuration including a data analysis unit 1, a communication monitoring unit 2, and a management information transmission unit 3. The data analysis unit 1 extracts predetermined information from each of a plurality of packets input to the own device, analyzes the predetermined information of the plurality of packets, and generates information relating to a characteristic of each flow of the packets, as flow management information. The communication monitoring unit 2 detects that an abnormality occurs in communication of packets in a communication network to which the own device is connected. When the abnormality detection unit 2 detects the abnormality, the management information transmission unit 3 transmits predetermined information already extracted from a predetermined packet input before the detection of the abnormality, as information for generating the flow management information expected to be generated by the own device, to a standby-system device.

Abstract: A connector comprises: contacts disposed in a row so as to be mutually parallel; a metal case that comprises one surface which is parallel to the direction of disposition of the contacts and two surfaces which are perpendicular with respect to the direction of disposition of the contacts and sandwich the ends of the disposition of the contacts, and that arranged while kept from contact with the contacts; and a synthetic-resin insulator that is formed so as to encase the contacts and the metal case and that exposes part of the contacts and part of the metal case as external contact points.

Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.

Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.

Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.

Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.

Abstract: Provided is a semiconductor device including: a first n-channel fin-type field effect transistor formed on a first crystal plane; and a second n-channel fin-type field effect transistor formed on the first crystal plane and having a gate length longer than that of the first n-channel fin-type field effect transistor. A side surface of a fin of the first n-channel fin-type field effect transistor and a side surface of a fin of the second n-channel fin-type field effect transistor are both formed on a second crystal plane having a carrier mobility lower than that of the first crystal plane. The width of the fin of the second n-channel fin-type field effect transistor is greater than the width of the fin of the first n-channel fin-type field effect transistor.

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.