Patents by Inventor Kiyotaka Kogo

Kiyotaka Kogo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10168505
    Abstract: An imaging apparatus includes an AF evaluation value calculation unit for calculating an AF evaluation value by integrating a focus differential signal value. The AF evaluation value calculation unit includes a high luminance region determination unit for extracting a feature of each pixel value and determining whether or not the feature is a backlight scene in a dark place, and a band determination unit for determining a band of a contour component of a subject. A focus differential signal value on a low luminance region side in a contour component formed by a boundary between a high luminance region and a low luminance region due to backlighting is excluded from the integration, and the AF evaluation value is calculated using only a focus differential signal value on the high luminance region side in the contour component of the subject to be focused as an object for the integration.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 1, 2019
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Kiyotaka Kogo
  • Publication number: 20180321464
    Abstract: An imaging apparatus includes an AF evaluation value calculation unit for calculating an AF evaluation value by integrating a focus differential signal value. The AF evaluation value calculation unit includes a high luminance region determination unit for extracting a feature of each pixel value and determining whether or not the feature is a backlight scene in a dark place, and a band determination unit for determining a band of a contour component of a subject. A focus differential signal value on a low luminance region side in a contour component formed by a boundary between a high luminance region and a low luminance region due to backlighting is excluded from the integration, and the AF evaluation value is calculated using only a focus differential signal value on the high luminance region side in the contour component of the subject to be focused as an object for the integration.
    Type: Application
    Filed: October 18, 2016
    Publication date: November 8, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: KIYOTAKA KOGO
  • Patent number: 8405445
    Abstract: In a complementary-MOSFET driving circuit for driving the charge multiplication gate of an EM-CCD, a ferrite bead is connected to a conduction-termination direction diode in parallel thereto, the conduction-termination direction diode being inserted into the gate electrodes of complementary MOSFETs in series therewith, the impedance of the ferrite bead at a switching frequency being lower than one-half of the gate-electrode impedance of the MOSFETs, a time during which the MOSFETs are brought into simultaneous conduction being shorter than ¼th of the switching period, the impedance of the ferrite bead at a frequency equivalent to ¼th of the switching period being higher than 2 times the gate-electrode impedance of the MOSFETs, a ferrite bead being connected to the drain electrodes of the complementary MOSFETs in series therewith, the impedance of the ferrite bead at the switching frequency being lower than one-half of the impedance of a capacitive load at the switching frequency, and the impedance of the ferr
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 26, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiko Nakamura, Yutaka Muto, Kiyotaka Kogo
  • Publication number: 20090295456
    Abstract: In a complementary-MOSFET driving circuit for driving the charge multiplication gate of an EM-CCD, a ferrite bead is connected to a conduction-termination direction diode in parallel thereto, the conduction-termination direction diode being inserted into the gate electrodes of complementary MOSFETs in series therewith, the impedance of the ferrite bead at a switching frequency being lower than one-half of the gate-electrode impedance of the MOSFETs, a time during which the MOSFETs are brought into simultaneous conduction being shorter than ¼th of the switching period, the impedance of the ferrite bead at a frequency equivalent to ¼th of the switching period being higher than 2 times the gate-electrode impedance of the MOSFETs, a ferrite bead being connected to the drain electrodes of the complementary MOSFETs in series therewith, the impedance of the ferrite bead at the switching frequency being lower than one-half of the impedance of a capacitive load at the switching frequency, and the impedance of the ferr
    Type: Application
    Filed: May 22, 2009
    Publication date: December 3, 2009
    Inventors: Kazuhiko NAKAMURA, Yutaka MUTO, Kiyotaka KOGO