Abstract: A semiconductor memory device has an aligner for aligning data. The aligner is disposed in front of a sense amplifier to directly receive data from an internal bus of a memory. This arrangement greatly reduces the time period from a data read to an arithmetic operation.

Abstract: A pipeline processor adapted for a microprocessor executes pipeline processes. The pipeline processes comprise the steps of reading a machine language instruction; decoding the read instruction; generating an address according to the decoded instruction; reading operand data from a cache memory according to the generated address; executing the instruction; and writing data into the cache memory. When the machine language instruction is a write instruction, the operand data reading step involves a process of searching the cache memory for the address where data is to be written. A result of the search is held in flag memories. Thereafter, the data writing step involves a process of referring to the flag memories, and is completed in one machine cycle.

Abstract: A content addressable memory (CAM) comprises a plurality of CAM cells, a CAM cell block comprising the CAM cells, a CAM array arranging a plurality of the CAM cell blocks to the row direction, a work line arranging a predetermined direction in each of the CAM cell blocks, a block matching line for outputting a result of a retrieval operation in the CAM cells connected to the same word line in the same CAM block and installed corresponding to the same word line, an array matching line for outputting the result of the retrieval operation output to the block matching line, and transfer circuits for transferring the result of the retrieval operation to the array matching line. Another CAM further comprises masking circuits for masking retrieval data at a predetermined CAM block.

Abstract: A microprocessor with on-cache memory and an address translation buffer in which it further comprises first and second flip-flop circuits for indicating in hit or miss in the tag field of the cache memory and for storing which of the X and Y sections of the tag field a target data exists. Access to the tag field is carried out prior to access to the data field of the cache memory, thereby preventing access to the data field when a miss occurs in the tag field, and thus decreasing power consumption.