Abstract: A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator includes a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal, a constant current circuit which generates a first control signal in accordance with the comparison result signal, a first delay circuit which generates a second control signal by delaying the comparison result signal, and a charge pump circuit which generates the boosted voltage in response to the first and second control signals.

Abstract: A semiconductor device is disclosed, which comprises a voltage dividing resistor circuit including a plurality of resistor elements connected in series between a power supply node and a ground node, a voltage detecting PMOS transistor having a gate connected to an output node of the voltage dividing resistor circuit and a source connected to the power supply node, a resistor element connected between a drain of the voltage detecting PMOS transistor and a ground node, a CMOS inverter circuit supplied with a power supply voltage through the power supply node, having an input terminal connected to a drain of the voltage detecting PMOS transistor and an output terminal for outputting a power-on detection signal, and a monitoring pad which monitors a potential of the output node of the voltage dividing resistor circuit from exterior of a semiconductor chip.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: A nonvolatile semiconductor memory device using a command control system comprises a protect cell composed of a nonvolatile memory cell, a protect sense amplifier circuit for reading the data from the protect cell, a high-voltage sensing circuit for supplying a voltage during a programmed operation such as a writing or an erasing operation, a protect control circuit for controlling the protect cell, and a control circuit for reading the data from the protect cell and according to the read-out data, controlling the command to the memory cell array.