Patents by Inventor Kiyotake Sakurai
Kiyotake Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742013Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: March 24, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20210210131Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 11004492Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: May 7, 2020Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10984848Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: February 18, 2020Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20200335147Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: ApplicationFiled: May 7, 2020Publication date: October 22, 2020Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10790004Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.Type: GrantFiled: December 12, 2018Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Takuya Nakanishi, Shinji Bessho
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Publication number: 20200194056Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Takuya Nakanishi, Shinji Bessho
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Patent number: 10685694Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: April 17, 2019Date of Patent: June 16, 2020Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20200185020Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10607678Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: February 6, 2019Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20190311757Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: ApplicationFiled: April 17, 2019Publication date: October 10, 2019Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20190287602Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: ApplicationFiled: February 6, 2019Publication date: September 19, 2019Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10311933Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: August 3, 2018Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10229727Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: March 13, 2018Date of Patent: March 12, 2019Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20190051343Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: ApplicationFiled: August 3, 2018Publication date: February 14, 2019Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10056129Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: August 10, 2017Date of Patent: August 21, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 8238181Abstract: A semiconductor device includes first and second lines, and a switch between the first and second lines. The switch temporary and electrically connects the first and second lines to each other, when the first signal line is transitioned from a first level to a second level while the second signal line is transitioned from the second level to the first level.Type: GrantFiled: January 27, 2010Date of Patent: August 7, 2012Assignee: Elpida Memory, Inc.Inventors: Tomohiro Ogasawara, Kiyotake Sakurai
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Publication number: 20100195417Abstract: A semiconductor device includes first and second lines, and a switch between the first and second lines. The switch temporary and electrically connects the first and second lines to each other, when the first signal line is transitioned from a first level to a second level while the second signal line is transitioned from the second level to the first level.Type: ApplicationFiled: January 27, 2010Publication date: August 5, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Tomohiro OGASAWARA, Kiyotake SAKURAI