Abstract: A motion vector search apparatus has two internal memories for storing one macroblock of current image data each and N internal memories for storing M macroblocks of reference image data each, where M and N are integers greater than one. Selectors feed data from one of the current image memories and N?1 of the reference image memories to a processor that carries out a block matching calculation, on the basis of which a detector finds a motion vector for the selected macroblock of current image data. During the search, data for one new current image macroblock and M new reference image macroblocks are read into the non-selected memories, so that as soon as the motion vector is found, the search for the next motion vector can begin.

Abstract: A motion vector search apparatus has two internal memories for storing one macroblock of current image data each and N internal memories for storing M macroblocks of reference image data each, where M and N are integers greater than one. Selectors feed data from one of the current image memories and N?1 of the reference image memories to a processor that carries out a block matching calculation, on the basis of which a detector finds a motion vector for the selected macroblock of current image data. During the search, data for one new current image macroblock and M new reference image macroblocks are read into the non-selected memories, so that as soon as the motion vector is found, the search for the next motion vector can begin.

Abstract: The present invention provides a semiconductor integrated circuit device easy to design timing to be provided with respect to an external memory. In the semiconductor integrated circuit device (10), a second memory controller (16) is provided outside a hard macro (12) containing a first memory controller (15). The length of a wiring (second wiring) between the second memory controller (16) and an IO pad unit (13) is set shorter than the length of a wiring (first wiring) between the first memory controller (15) and the IO pad unit (13). Further, a wiring (40) is provided which transmits a switch signal for exclusively switching the states of the first memory controller (15) and the second memory controller (16) to either one of valid and invalid states.

Abstract: An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to an external bus EXBUS respectively. The bus controllers 15, 16 respectively output external bus use request signals BRQ1 and BRQ2, and obtain the right for using the external bus EXBUS. When the bus controllers 15, 16 end use of the external bus EXBUS, the bus controllers 15, 16 stop to output the external bus use request signals BRQ1 and BRQ2 and output off-time signals OFT1 and OFT2 immediately thereafter.

Abstract: The present invention provides a semiconductor integrated circuit device easy to design timing to be provided with respect to an external memory. In the semiconductor integrated circuit device (10), a second memory controller (16) is provided outside a hard macro (12) containing a first memory controller (15). The length of a wiring (second wiring) between the second memory controller (16) and an IO pad unit (13) is set shorter than the length of a wiring (first wiring) between the first memory controller (15) and the IO pad unit (13). Further, a wiring (40) is provided which transmits a switch signal for exclusively switching the states of the first memory controller (15) and the second memory controller (16) to either one of valid and invalid states.

Abstract: An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to an external bus EXBUS respectively. The bus controllers 15, 16 respectively output external bus use request signals BRQ1 and BRQ2, and obtain the right for using the external bus EXBUS. When the bus controllers 15, 16 end use of the external bus EXBUS, the bus controllers 15, 16 stop to output the external bus use request signals BRQ1 and BRQ2 and output off-time signals OFT1 and OFT2 immediately thereafter.

Abstract: A memory device has a main memory circuit, an auxiliary memory circuit for storing test data, and an interface circuit for transferring test data between the auxiliary memory circuit and external test equipment. Test data are transferred from the external test equipment to the auxiliary memory circuit, then transferred repeatedly to different locations in the main memory circuit. Different test patterns are generated by selectively inverting one bit, or all bits, in the test data as the data are transferred into the main memory circuit. Test results are obtained by using a comparator in the memory device to compare the data stored in the auxiliary memory circuit with data read from the main memory circuit.