Patents by Inventor Kiyotaro Itagaki
Kiyotaro Itagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862254Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.Type: GrantFiled: August 24, 2021Date of Patent: January 2, 2024Assignee: Kioxia CorporationInventors: Dongxu Li, Kiyotaro Itagaki, Kazuaki Kawaguchi
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Publication number: 20220270690Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.Type: ApplicationFiled: August 24, 2021Publication date: August 25, 2022Applicant: Kioxia CorporationInventors: Dongxu LI, Kiyotaro ITAGAKI, Kazuaki KAWAGUCHI
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Patent number: 11295794Abstract: According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.Type: GrantFiled: February 9, 2021Date of Patent: April 5, 2022Assignee: KIOXIA CORPORATIONInventor: Kiyotaro Itagaki
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Publication number: 20210166743Abstract: According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Applicant: Kioxia CorporationInventor: Kiyotaro ITAGAKI
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Patent number: 9490019Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.Type: GrantFiled: April 23, 2015Date of Patent: November 8, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kiyotaro Itagaki
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Patent number: 9437307Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.Type: GrantFiled: October 13, 2014Date of Patent: September 6, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kiyotaro Itagaki, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
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Publication number: 20150228347Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.Type: ApplicationFiled: April 23, 2015Publication date: August 13, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kiyotaro ITAGAKI
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Patent number: 9036411Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.Type: GrantFiled: May 30, 2012Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kiyotaro Itagaki
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Patent number: 8982630Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.Type: GrantFiled: May 30, 2014Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Norichika Asaoka, Masanobu Shirakawa, Kiyotaro Itagaki
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Publication number: 20150029791Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.Type: ApplicationFiled: October 13, 2014Publication date: January 29, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiyotaro ITAGAKI, Masaru KITO, Ryu OGIWARA, Hitoshi IWAI
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Publication number: 20140334231Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiyotaro ITAGAKI, Kunihiro YAMADA, Yoshihisa IWATA
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Patent number: 8873296Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.Type: GrantFiled: July 29, 2013Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiyotaro Itagaki, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
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Patent number: 8873330Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.Type: GrantFiled: March 12, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Fumihiro Kono, Kiyotaro Itagaki
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Publication number: 20140269073Abstract: An aspect of the present embodiment, there is provided a semiconductor memory device including memory cell arrays, each of the memory cell arrays including memory cells, including a clock generator configured to generate clock, an input-output circuit configured to input and output data, buses, a portion of each of the buses crossing the memory cell arrays, switches, each of the switches being placed in the bus, control circuit configured to control the switches to generate a path which transfers clock and data without overlapping with an activated memory cell as viewed from above.Type: ApplicationFiled: September 9, 2013Publication date: September 18, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kiyotaro ITAGAKI
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Publication number: 20140269084Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norichika ASAOKA, Masanobu Shirakawa, Kiyotaro Itagaki
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Patent number: 8817538Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.Type: GrantFiled: June 11, 2012Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiyotaro Itagaki, Kunihiro Yamada, Yoshihisa Iwata
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Patent number: 8767466Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.Type: GrantFiled: March 14, 2012Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Norichika Asaoka, Masanobu Shirakawa, Kiyotaro Itagaki
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Publication number: 20140063963Abstract: According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed.Type: ApplicationFiled: March 14, 2013Publication date: March 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Xu Li, Kiyotaro Itagaki, Ryo Fukuda
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Patent number: 8605508Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.Type: GrantFiled: May 4, 2012Date of Patent: December 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kiyotaro Itagaki, Yoshihisa Iwata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Ryota Katsumata, Hideaki Aochi, Akihiro Nitayama, Takashi Maeda, Tomoo Hishida
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Patent number: RE45890Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.Type: GrantFiled: October 23, 2014Date of Patent: February 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kiyotaro Itagaki, Yoshiaki Fukuzumi, Yoshihisa Iwata, Ryota Katsumata