Patents by Inventor Kiyotaro Itagaki

Kiyotaro Itagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9490019
    Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: November 8, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kiyotaro Itagaki
  • Patent number: 9437307
    Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro Itagaki, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
  • Publication number: 20150228347
    Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kiyotaro ITAGAKI
  • Patent number: 9036411
    Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kiyotaro Itagaki
  • Patent number: 8982630
    Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norichika Asaoka, Masanobu Shirakawa, Kiyotaro Itagaki
  • Publication number: 20150029791
    Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
    Type: Application
    Filed: October 13, 2014
    Publication date: January 29, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro ITAGAKI, Masaru KITO, Ryu OGIWARA, Hitoshi IWAI
  • Publication number: 20140334231
    Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
    Type: Application
    Filed: July 23, 2014
    Publication date: November 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro ITAGAKI, Kunihiro YAMADA, Yoshihisa IWATA
  • Patent number: 8873296
    Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
  • Patent number: 8873330
    Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Kono, Kiyotaro Itagaki
  • Publication number: 20140269084
    Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Norichika ASAOKA, Masanobu Shirakawa, Kiyotaro Itagaki
  • Publication number: 20140269073
    Abstract: An aspect of the present embodiment, there is provided a semiconductor memory device including memory cell arrays, each of the memory cell arrays including memory cells, including a clock generator configured to generate clock, an input-output circuit configured to input and output data, buses, a portion of each of the buses crossing the memory cell arrays, switches, each of the switches being placed in the bus, control circuit configured to control the switches to generate a path which transfers clock and data without overlapping with an activated memory cell as viewed from above.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kiyotaro ITAGAKI
  • Patent number: 8817538
    Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Kunihiro Yamada, Yoshihisa Iwata
  • Patent number: 8767466
    Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norichika Asaoka, Masanobu Shirakawa, Kiyotaro Itagaki
  • Publication number: 20140063963
    Abstract: According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Xu Li, Kiyotaro Itagaki, Ryo Fukuda
  • Patent number: 8605508
    Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Yoshihisa Iwata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Ryota Katsumata, Hideaki Aochi, Akihiro Nitayama, Takashi Maeda, Tomoo Hishida
  • Publication number: 20130314994
    Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
    Type: Application
    Filed: July 29, 2013
    Publication date: November 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro ITAGAKI, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
  • Patent number: 8531901
    Abstract: A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Hitoshi Iwai, Kiyotaro Itagaki
  • Patent number: 8514627
    Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Masaru Kito, Ryu Ogiwara, Hitoshi Iwai
  • Publication number: 20130077401
    Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
    Type: Application
    Filed: March 12, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Kono, Kiyotaro Itagaki
  • Patent number: RE45890
    Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro Itagaki, Yoshiaki Fukuzumi, Yoshihisa Iwata, Ryota Katsumata