Patents by Inventor Kiyoto Ito
Kiyoto Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170094200Abstract: An image processing apparatus performs fast image transfer of an image sensor and can easily satisfy required performance of image transfer. The image processing apparatus includes a sensor and a processing unit, the sensor obtains a first image including a recognition target at a first time, obtains a second image including the recognition target at a second time later than the first time, and obtains a third image including the recognition target at a third time later than the second time, and the processing unit determines first setting information of the sensor from the first image and the second image so as to satisfy a predetermined condition when the third image is obtained. Furthermore, the first setting information includes a dimension of the third image and a frame rate at the time of obtaining the third image.Type: ApplicationFiled: May 21, 2014Publication date: March 30, 2017Applicant: HITACHI, LTD.Inventors: Takashi SAEGUSA, Kiyoto ITO, Toyokazu TAKAGI, Tomohiro INOUE
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Patent number: 9144908Abstract: A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.Type: GrantFiled: April 18, 2012Date of Patent: September 29, 2015Assignee: Hitachi, Ltd.Inventors: Makoto Saen, Kiyoto Ito, Yoshimitsu Yanagawa, Tomomi Takahashi
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Patent number: 8698140Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.Type: GrantFiled: March 15, 2010Date of Patent: April 15, 2014Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Takanobu Tsunoda, Makoto Saen
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Publication number: 20130079905Abstract: In a human-operated working machine system made up of a working machine including an actuator and an operating device, various operations for target objects having various hardnesses and shapes are achieved at a speed not giving stress to an operator. To this end, the working machine has a control structure in which a control program corresponding to an action content is executed with both of displacement information with respect to the working machine inputted from the operating device and information from a sensor of the working machine being taken as inputs. Furthermore, the operating device has a simulator that predicts an action of the working machine so as to quickly provide image information and tactile information regarding the action of the working machine to the operator.Type: ApplicationFiled: June 3, 2010Publication date: March 28, 2013Applicant: HITACHI, LTD.Inventors: Makoto Saen, Kiyoto Ito
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Publication number: 20120280231Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.Type: ApplicationFiled: March 15, 2010Publication date: November 8, 2012Inventors: Kiyoto Ito, Takanobu Tsunoda, Makoto Saen
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Patent number: 8242589Abstract: In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods.Type: GrantFiled: February 27, 2009Date of Patent: August 14, 2012Assignee: Hitachi, Ltd.Inventors: Makoto Saen, Kenichi Osada, Kiyoto Ito
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Patent number: 8125059Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.Type: GrantFiled: October 29, 2009Date of Patent: February 28, 2012Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Koji Hosogi, Takanobu Tsunoda
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Publication number: 20110309359Abstract: In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods.Type: ApplicationFiled: February 27, 2009Publication date: December 22, 2011Inventors: Makoto Saen, Kenichi Osada, Kiyoto Ito
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Patent number: 7977781Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.Type: GrantFiled: October 30, 2010Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Makoto Saen, Yuki Kuroda
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Publication number: 20110042825Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.Type: ApplicationFiled: October 30, 2010Publication date: February 24, 2011Inventors: KIYOTO ITO, Makoto Saen, Yuki Kuroda
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Patent number: 7834440Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.Type: GrantFiled: May 14, 2009Date of Patent: November 16, 2010Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Makoto Saen, Yuki Kuroda
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Publication number: 20100109133Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Inventors: KIYOTO ITO, Koji HOSOGI, Takanobu TSUNODA
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Publication number: 20100078635Abstract: As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path.Type: ApplicationFiled: May 14, 2009Publication date: April 1, 2010Inventors: Yuki Kuroda, Makoto Saen, Hiroyuki Mizuno, Kiyoto Ito
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Publication number: 20100078790Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.Type: ApplicationFiled: May 14, 2009Publication date: April 1, 2010Inventors: Kiyoto ITO, Makoto Saen, Yuki Kuroda
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Patent number: 7397951Abstract: SRAMs A, B, C, and D having pixel data of each small block of each large block, for example a small block Aij for the SRAM A, to simultaneously read out a plurality of pixel data in the small block by specifying an address assigned to each small block, and a matrix of coefficient in which a matrix of plural coefficients are arranged are provided. Also provided are a coefficient matrix controller 12 and an adding section 13 to multiply the plural coefficients respectively by pixel data corresponding to each thereof and obtain a sum of the multiplied results. Each pixel data of each small block forming one large block, the pixel data being read out from the SRAMs A, B, C, and D, are multiplied by the coefficient matrix rearranged into a predetermined order.Type: GrantFiled: February 6, 2004Date of Patent: July 8, 2008Assignee: Rohm Co., Ltd.Inventors: Makoto Ogawa, Kiyoto Ito, Tadashi Shibata
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Publication number: 20040172436Abstract: SRAMs A, B, C, and D having pixel data of each small block of each large block, for example a small block Aij for the SRAM A, to simultaneously read out a plurality of pixel data in the small block by specifying an address assigned to each small block, and a matrix of coefficient in which a matrix of plural coefficients are arranged are provided. Also provided are a coefficient matrix controller 12 and an adding section 13 to multiply the plural coefficients respectively by pixel data corresponding to each thereof and obtain a sum of the multiplied results. Each pixel data of each small block forming one large block, the pixel data being read out from the SRAMs A, B, C, and D, are multiplied by the coefficient matrix rearranged into a predetermined order.Type: ApplicationFiled: February 6, 2004Publication date: September 2, 2004Inventors: Makoto Ogawa, Kiyoto Ito, Tadashi Shibata