Abstract: A dummy circuit (303) is basically configured in the same manner as level shift circuits (203a, 203b), but an HVNMOS (311) of the dummy circuit is always set at a non-conducting state. A mask circuit (403) removes noise in signals (S200a, S200b) outputted from the level shift circuits (203a, 203b), respectively, using a signal (S300) outputted from the dummy circuit (303). Control signals (S100a, S100b) include iterative pulses that are transmitted to S and R inputs of an RS flip-flop (502). PMOSs (215, 225) bring current paths (210, 220) into a non-conducting state in response to an output signal (S500) from the RS flip-flop (502) to thereby suspend one of the level shift circuits (203a, 203b).

Abstract: A dummy circuit (303) is basically configured in the same manner as level shift circuits (203a, 203b), but an HVNMOS (311) of the dummy circuit is always set at a non-conducting state. A mask circuit (403) removes noise in signals (S200a, S200b) outputted from the level shift circuits (203a, 203b), respectively, using a signal (S300) outputted from the dummy circuit (303). Control signals (S100a, S100b) include iterative pulses that are transmitted to S and R inputs of an RS flip-flop (502). PMOSs (215, 225) bring current paths (210, 220) into a non-conducting state in response to an output signal (S500) from the RS flip-flop (502) to thereby suspend one of the level shift circuits (203a, 203b).

Abstract: A high resistance n-type base layer is formed on a silicon substrate with an insulating layer made of a silicon oxide film therebetween. In the high resistance n-type base layer a p-ch MOS transistor is formed. The p-ch MOS transistor is electrically isolated from another element by trench isolation formed of a trench. A p+ source layer in the p-ch MOS transistor surrounds a periphery of a p+ drain layer and has, for example, an elliptical planar configuration. A semiconductor device thus formed has a high drive capacity and is suitable to high integration.

Abstract: A pulse generation circuit which can be controlled to generate on-signals and off-signals simultaneously for use in testing the protection circuit of a power device's drive circuitry. The protection circuit prevents faulty operation due to dv/dt transient signals which can cause the S and R input signals to a set-reset flip-flop circuit to simultaneously be HI, resulting in an error condition. Protection circuit 26a has the structure as shown in FIG. 1. A pulse generation circuit, as shown in FIG. 3, can be used to provide simultaneous changes of logic value at B and C to test the protection circuit.

Abstract: The present invention provides a protection circuit which prevents set signals and reset signals from inputting simultaneously to a set-reset-flip-flap circuit, and a pulse generation circuit which generates tentatively on-signals and off-signals simultaneously, in a semiconductor device having a drive circuit of the power device which prevents faulty operation by dv/dt transient signals.

Abstract: An ON-state voltage is reduced. A line of gate trenches 8 is formed on an n-type silicon layer (a SOI layer) 3 so as to divide a p-type base layer 4 and an n-type emitter layer 5. The gate trench 8 extends from the n-type emitter layer 5 toward a collector electrode 21. A gate electrode 10 is buried in the gate trench 8 with a gate insulation film 9 interposed therebetween. The gate electrode 10 is provided opposite to a vertical section of the p-type base layer 4. Therefore, a channel width can be kept great. Furthermore, a wide region of the n-type silicon layer 3 which is provided opposite to the gate trench 8 functions as an accumulation layer of a hole. As a result, the ON-state voltage can be reduced.

Abstract: A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Abstract: The present invention is mainly characterized in that a Bi-CMOS is obtained in which characteristics of a bipolar transistor are not deteriorated. The device includes a bipolar transistor and a CMOSFET formed on a semiconductor substrate separately from each other by a field oxide film. The thickness of a gate electrode of an NMOSFET and a gate electrode of a PMOSFET is made larger than the thickness of an emitter electrode of the bipolar transistor.

Abstract: A high-concentration n-type buffer layer and a low-concentration n-type buffer layer are provided between a p-type collector layer and a high-resistance n-type base layer, and respective impurity concentrations of the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are set so that concentrations of carriers that propagate through the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are in excess of the respective impurity concentrations thereof in an ON state. Thus, an insulated gate bipolar transistor having excellent withstand voltage, ON-state voltage and turn-off characteristics is obtained.

Abstract: A semiconductor device which allows an ON-state voltage to be lower than that of a conventional device and a method of manufacturing such a device. In this semiconductor device, a gate electrode is formed to have a planar area of its region covering a first base layer larger than that of its region covering a second base layer, thereby increasing a cathode short-circuit ratio of a cathode-shorted diode equivalent to this semiconductor device. As a result, a lower voltage than conventional ON-state can be obtained.

Abstract: It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.

Abstract: The present invention is mainly characterized in that a Bi-CMOS is obtained in which characteristics of a bipolar transistor are not deteriorated. The device includes a bipolar transistor and a CMOSFET formed on a semiconductor substrate separately from each other by a field oxide film. The thickness of a gate electrode of an NMOSFET and a gate electrode of a PMOSFET is made larger than the thickness of an emitter electrode of the bipolar transistor.

Abstract: A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film.

Abstract: A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film.

Abstract: In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

Abstract: Conductive layers (5a, 8a) included in a multi-layer structure (30a) are electrically interconnected through an conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) existing under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).

Abstract: A method of fabricating a MOS field effect semiconductor device having an LLD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Abstract: Conductive layers (5a, 9a) included in a multi-layer structure (30a) are electrically interconnected through a conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) exisitng under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).

Abstract: A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by unisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.