Patents by Inventor Kiyotoshi Nakagawa

Kiyotoshi Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage MOS transistor
    Patent number: 4947232
    Abstract: A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.
    Type: Grant
    Filed: November 28, 1988
    Date of Patent: August 7, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsutomu Ashida, Kiyotoshi Nakagawa, Katsumasa Fujii, Yasuo Torimaru
  • High voltage MOS field effect semiconductor device
    Patent number: 4926243
    Abstract: A high voltage MOS field-effect semiconductor device comprising, as formed on a single seimconductor substrate a high voltage first MOS field-effect transistor and a conventional second MOS field-effect transistor operable at a lower voltage than the first transistor. The semiconductor substrate is covered with an aluminum or like conductor layer over the region thereof where the conventional second field-effect transistor is located.
    Type: Grant
    Filed: March 9, 1988
    Date of Patent: May 15, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyotoshi Nakagawa, Kenzo Kawano
  • High voltage MOS transistor
    Patent number: 4766474
    Abstract: A MOS transistor is featured by providing mult-layered covering elements for covering a channel region of the semiconductor device. Each of the covering elements is interposed by an insulating layer. Preferably, the covering layers comprise first and second covering layers neither of which are connected to either of the drain electrode, the source electrode, or the gate electrode. A field plate layer, as a third covering layer, is disposed over the first and second covering layers.
    Type: Grant
    Filed: May 27, 1981
    Date of Patent: August 23, 1988
    Assignee: Sharp Kabushiki Kiasha
    Inventors: Kiyotoshi Nakagawa, Katsumi Miyano, Takeo Fujimoto
  • High voltage MOS transistor
    Patent number: 4757362
    Abstract: A MOS transistor is featured by the provision of a conductive covering element for covering a drift channel region of the semiconductor device. The covering element is interposed by an insulating layer which is relatively thick. The covering element comprises a floating conductive element, disposed on the insulating layer, and a field plate means, disposed on a second insulating layer.
    Type: Grant
    Filed: May 27, 1981
    Date of Patent: July 12, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetuo Biwa, Kiyotoshi Nakagawa
  • Improved high voltage MOS transistor with field plate layers for preventing reverse field plate effect
    Patent number: 4614959
    Abstract: A metal oxide semiconductor device is featured by the provision of at least two field plate elements interposed by an insulating layer. The field plate elements are connected from a drain electrode and a source electrode. Otherwise, they are isolated from the respective drain electrode, source electrode, and gate electrode. Each of the field plate elements consists of Al, polycrystalline silicon, or the like. An extensive conductive layer is provided which overlaps vertically each of the field plate elements.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: September 30, 1986
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kiyotoshi Nakagawa