Patents by Inventor Kiyotoshi Ueda

Kiyotoshi Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6733182
    Abstract: To provide a rolling bearing for a man-made satellite which is free from the damages, e.g., formation of the band mark on the surfaces of the rolling elements, and the losing of the luster of the surfaces thereof. There is provided a rolling bearing, which is used mainly for a man-made satellite, includes an outer ring, an inner ring, and rolling elements. The parent material of those components is martensitic stainless steel. Of those components, at least the rolling elements are processed to have nitride surface layers formed over their surfaces. A hardness of the nitride surface layer is Hv1200 to 1500.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: May 11, 2004
    Assignee: NSK Ltd.
    Inventors: Kiyotoshi Ueda, Yukio Ohura, Susumu Tanaka
  • Publication number: 20030016041
    Abstract: A semiconductor integrated circuit testing apparatus of the invention comprises a correcting means for correcting input waveform timing of a measuring signal applied to all pins of a semiconductor integrated circuit 5. The correcting means includes: a high-speed clock generating circuit 12 for generating a clock signal; latch circuits 9a, 9b for latching the measuring signal by use of the clock signal from the high-speed clock generating circuit 12; FIFO memories 10a, 10b for storing as data the measuring signal latched by the latch circuits 9a, 9b; and a control circuit 14 for retrieving the data from the FIFO memories 10a, 10b for transfer to a tester.
    Type: Application
    Filed: January 23, 2001
    Publication date: January 23, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyotoshi Ueda, Shoichi Ooshita
  • Publication number: 20020061150
    Abstract: To provide a rolling bearing for a man-made satellite which is free from the damages, e.g., formation of the band mark on the surfaces of the rolling elements, and the losing of the luster of the surfaces thereof. There is provided a rolling bearing, which is used mainly for a man-made satellite, includes an outer ring, an inner ring, and rolling elements. The parent material of those components is martensitic stainless steel. Of those components, at least the rolling elements are processed to have nitride surface layers formed over their surfaces. A hardness of the nitride surface layer is Hv1200 to 1500.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 23, 2002
    Applicant: NSK LTD.
    Inventors: Kiyotoshi Ueda, Yukio Ohura, Susumu Tanaka
  • Patent number: 5961222
    Abstract: An anti-electrolytic corrosion rolling bearing having at least an outer race, an inner race, and rolling elements interposed between the outer and inner races, which has an insulating body on at least one of the outer peripheral surface of the outer race, the inner peripheral surface of the inner race, and the side surfaces of the outer race and inner race, said insulating body being composed of an insulating film or insulating member each containing at least one of a thermoplastic synthetic resin, a rubber, and a thermoplastic elastomer as a base material and having a resistivity of not less than 1.times.10.sup.13 .OMEGA..multidot.cm and a thermal conductivity of not less than 0.5 W/m.multidot.K.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: October 5, 1999
    Assignee: NSK Ltd.
    Inventors: Toshikazu Yabe, Toshimi Takajo, Fumio Ueki, Takahiko Uchiyama, Shigeaki Abe, Takanori Yamada, Magozou Hamamoto, Kiyotoshi Ueda, Yasuhisa Terada, Yukio Ohura
  • Patent number: 5386189
    Abstract: An IC measuring method including positioning a plurality of ICS, each having a plurality of circuit blocks performing different functions, selecting different circuit blocks in each of the plurality of ICs, measuring the test results from each of the selected circuit blocks, and selecting a different circuit block in each of the plurality of ICs for the next measurement. The circuit block selection is controlled by a matrix circuit or by physically shifting the positions of the ICs.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: January 31, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Nishimura, Kiyotoshi Ueda
  • Patent number: 5367263
    Abstract: A semiconductor integrated circuit device includes individual circuit blocks which are tested according to the method of the invention. Circuit blocks of a semiconductor integrated circuit device may be tested independently of one another until all circuit blocks have been tested, or alternatively may be simultaneously tested. The multi-test method of the invention simultaneously tests plural semiconductor integrated circuit devices by successively testing corresponding circuit blocks on each semiconductor integrated circuit device. The test apparatus of the present invention is of minimal size and complexity, and greatly enhances testability of a semiconductor integrated circuit device.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: November 22, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyotoshi Ueda, Kazuhiro Nishimura