Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.

Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.

Abstract: A current limiter includes: a P type MOS transistor electrically coupled between a main power potential supply line supplying power supply potential Vcc and a power potential supply line; and a level converter generating a control signal of signal levels in an operating state and a standby state, respectively, corresponding to a ground potential Vss and an intermediate potential Vhh (Vss<Vhh<Vcc) adjustable externally. The control signal is inputted into the gate of the transistor. The transistor supplies a sufficient operating current for ensuring an operating margin and a standby current of a prescribed value or less satisfying a requirement for lower power consumption onto the power potential supply line in the operating state and the standby state, respectively.

Abstract: A current limiter includes: a P type MOS transistor electrically coupled between a main power potential supply line supplying power supply potential Vcc and a power potential supply line; and a level converter generating a control signal of signal levels in an operating state and a standby state, respectively, corresponding to a ground potential Vss and an intermediate potential Vhh (Vss<Vhh<Vcc) adjustable externally. The control signal is inputted into the gate of the transistor. The transistor supplies a sufficient operating current for ensuring an operating margin and a standby current of a prescribed value or less satisfying a requirement for lower power consumption onto the power potential supply line in the operating state and the standby state, respectively.

Abstract: A memory cell power supply line is provided to supply a ground potential corresponding to each column in a regular memory cell array. Among fuse elements, the fuse element corresponding to the memory cell column that is to be subjected to redundancy replacement is decoupled, whereby supply of the ground potential to the regular memory cell column to be replaced is suppressed.

Abstract: A semiconductor device prevents latch up and enables subminiaturization of its structure, and a method can manufacture the semiconductor device. In the semiconductor device containing field-effect transistors of a complementary type, an interconnection containing semiconductor having n-type impurity connects a p-type impurity diffusion region forming an emitter electrode of a parasitically formed bipolar transistor to an n-type impurity diffusion region electrically connected to a power supply line. Thereby, a pn junction operating as a rectifier element is formed at a contact region between a connection portion and the p-type impurity diffusion region.

Abstract: A word line activation signal generated by a timing generator is surely at L level in a prescribed period regardless of the power supply voltage. A row address signal delayed by a delay circuit in a row address buffer changes in a period in which the word line activation signal is at L level. Accordingly, even if skew occurs, a non-selected word line is never activated. Consequently, it is possible to prevent delay of access to a memory cell and erroneous writing to a memory cell.

Abstract: An improved SRAM is disclosed including a plurality of memory blocks each having a redundancy memory cell to be shared. In redundancy row decoders 50a, 50b, 50c provided in each memory block, a memory block to be remedied is programmed. Accordingly, a redundancy memory cell row corresponding to each redundancy row decoder can be used for remedy of a defect memory cell in another memory block. Since a defect memory cell may be remedied flexibly, the yield rate in production of semiconductor memories is improved.