Patents by Inventor Kizashi Shimada

Kizashi Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5374835
    Abstract: A compound semiconductor device such as HEMTs (High Electron Mobility Transistors), metal semiconductor field effect transistors, and the like includes a compound semiconductor substrate having an active region, an insulating film provided over the semiconductor substrate, source and drain electrodes provided on the active region, and a gate electrode located between the source and drain electrodes. In the structure, the gate electrode has a lower electrode portion for providing a Schottky barrier contact with the active region through an opening of the insulating film, and an upper electrode portion provided on the insulating film to extend toward only the drain electrode.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: December 20, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Mayumi Kamura, Tatsuo Akiyama
  • Patent number: 5229323
    Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: July 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 5049954
    Abstract: A Schottky gate electrode structure of a GaAs field effect semiconductor device comprises a Ti film having a thickness of 2 nm to 25 nm and provided adherently on a GaAs substrate including source and drain regions, and a refractory electrode film provided on the Ti film and formed of a material selected from W, Mo, Cr, Ta, Nb, V, Hf, Zr, nitrides of these metals, silicides of these metals, carbides of these metals, Ti-W alloys, WSixNy, TiNx, and TiSix. Adhesion of the refractory electrode film to the GaAs substrate is increased, and heat resisting properties of Schottky characteristics are improved according to the thin Ti film.
    Type: Grant
    Filed: December 5, 1989
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 4700455
    Abstract: A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.
    Type: Grant
    Filed: October 30, 1985
    Date of Patent: October 20, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino