Patents by Inventor Kizashi Tanioka

Kizashi Tanioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187279
    Abstract: A method for manufacturing a semiconductor device includes forming a first stacked body having a plurality of first material films and a plurality of second material films that are alternately stacked, in a divided region of a semiconductor wafer including a chip region in which a semiconductor element is provided and the divided region between the adjacent chip regions, a plurality of times in a normal line direction of a substrate surface of the semiconductor wafer. The semiconductor wafer is fragmented by a blade having a width wider than the width of the first stacked body.
    Type: Application
    Filed: August 24, 2022
    Publication date: June 15, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Takanobu ONO, Masaki SEKINE, Kizashi TANIOKA, Takaaki AKAHANE
  • Patent number: 11152345
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes forming a slit in a first wafer in which a first semiconductor layer is formed on a first substrate, sticking together the first wafer in which the slit is formed and a second wafer in which a second semiconductor layer is formed on a second substrate, the sticking being performed between a side of the first semiconductor layer and a side of the second semiconductor layer, thinning the first substrate or the second substrate of a member obtained by the sticking, forming an interconnection on a face of the substrate that is thinned, and dicing a member on which the interconnection is formed in accordance with a position of the slit.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 19, 2021
    Assignee: Kioxia Corporation
    Inventor: Kizashi Tanioka
  • Publication number: 20210082900
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes forming a slit in a first wafer in which a first semiconductor layer is formed on a first substrate, sticking together the first wafer in which the slit is formed and a second wafer in which a second semiconductor layer is formed on a second substrate, the sticking being performed between a side of the first semiconductor layer and a side of the second semiconductor layer, thinning the first substrate or the second substrate of a member obtained by the sticking, forming an interconnection on a face of the substrate that is thinned, and dicing a member on which the interconnection is formed in accordance with a position of the slit.
    Type: Application
    Filed: February 24, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventor: Kizashi TANIOKA
  • Publication number: 20100164125
    Abstract: A method of evaluating the flame retardancy of a sealing resin comprises a step of fusion cutting a heating element by causing the heating element to generate heat by the passage of electric current to a test sample of a molded body of the sealing resin including the heating element therein; a step of igniting the sealing resin by continuing the passage of electric current even after the heating element is fusion-cut; and a step of measuring voltage and/or current applied in a period from when the heating element is fusion-cut to the ignition of the sealing resin. The test sample is used in the method of evaluating the flame retardancy and provided with a heating wire; conducting terminals made of metal having an electric resistance lower than the heating wire and connected to both ends of the heating wire; and a sealing resin layer covering the outer periphery of the heating wire.
    Type: Application
    Filed: December 17, 2009
    Publication date: July 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kizashi Tanioka, Masanori Okamoto, Akiko Suda