Patents by Inventor Kjeld Svendsen
Kjeld Svendsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220004501Abstract: An apparatus configured to provide just-in-time synonym handling, and related systems, methods, and computer-readable media, are disclosed. The apparatus includes a first cache comprising a translation lookaside buffer (TLB) and a hit/miss block. The first cache is configured to form a miss request associated with an access to the first cache and provide the miss request to a second cache. The miss request comprises a physical address provided by the TLB and miss information provided by the hit/miss block. The first cache is further configured to receive, from the second cache, previously-stored metadata associated with an entry in the second cache. The entry in the second cache is associated with the miss request.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Inventors: John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Kjeld Svendsen, Bret Leslie Toll
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Patent number: 10691462Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads.Type: GrantFiled: December 14, 2017Date of Patent: June 23, 2020Assignee: ARM Finance Overseas LimitedInventor: Kjeld Svendsen
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Patent number: 10613984Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.Type: GrantFiled: April 19, 2018Date of Patent: April 7, 2020Assignee: AMPERE COMPUTING LLCInventor: Kjeld Svendsen
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Patent number: 10372615Abstract: Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.Type: GrantFiled: September 22, 2017Date of Patent: August 6, 2019Assignee: AMPERE COMPUTING LLCInventors: Kjeld Svendsen, John Gregory Favor
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Patent number: 10296341Abstract: A processor and system for latest producer tracking In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies in-register status values stored in the register rename map based on producer tracking status values stored in the producer tracking map. The producer tracking status values stored in the producer tracking map are modified based on buffer identification values output by the results buffer allocater circuit.Type: GrantFiled: May 5, 2015Date of Patent: May 21, 2019Assignee: ARM Finance Overseas LimitedInventors: Kjeld Svendsen, Xing Yu Jiang
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Patent number: 10191868Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.Type: GrantFiled: March 12, 2018Date of Patent: January 29, 2019Assignee: AMPERE COMPUTING LLCInventors: Kjeld Svendsen, Millind Mittal, Gaurav Singh
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Publication number: 20180239706Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Inventor: Kjeld Svendsen
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Publication number: 20180203810Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Inventors: Kjeld Svendsen, Millind Mittal, Gaurav Singh
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Patent number: 9971693Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.Type: GrantFiled: May 13, 2015Date of Patent: May 15, 2018Assignee: Ampere Computing LLCInventor: Kjeld Svendsen
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Publication number: 20180107486Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Inventor: Kjeld Svendsen
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Patent number: 9928183Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.Type: GrantFiled: September 26, 2014Date of Patent: March 27, 2018Assignee: Ampere Computing LLCInventors: Kjeld Svendsen, Millind Mittal, Gaurav Singh
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Patent number: 9851975Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads.Type: GrantFiled: September 23, 2014Date of Patent: December 26, 2017Assignee: ARM Finance Overseas LimitedInventor: Kjeld Svendsen
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Patent number: 9798672Abstract: Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.Type: GrantFiled: April 14, 2016Date of Patent: October 24, 2017Assignee: MACOM CONNECTIVITY SOLUTIONS, LLCInventors: Kjeld Svendsen, John Gregory Favor
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Patent number: 9734072Abstract: Provided is an integrated circuit that includes a first prefetcher component communicatively coupled to a processor and a second prefetcher component communicatively coupled to the memory controller. The first prefetcher component configured for sending prefetch requests to the memory controller. The second prefetcher component configured for accessing prefetch data based on the prefetch request and storing the prefetch data in a prefetch cache of the memory controller.Type: GrantFiled: March 24, 2015Date of Patent: August 15, 2017Assignee: MACOM CONNECTIVITY SOLUTIONS, LLCInventor: Kjeld Svendsen
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Patent number: 9558123Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.Type: GrantFiled: May 18, 2016Date of Patent: January 31, 2017Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventor: Kjeld Svendsen
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Publication number: 20160335186Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventor: Kjeld Svendsen
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Publication number: 20160283383Abstract: Provided is an integrated circuit that includes a first prefetcher component communicatively coupled to a processor and a second prefetcher component communicatively coupled to the memory controller. The first prefetcher component configured for sending prefetch requests to the memory controller. The second prefetcher component configured for accessing prefetch data based on the prefetch request and storing the prefetch data in a prefetch cache of the memory controller.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Inventor: Kjeld Svendsen
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Publication number: 20160259730Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.Type: ApplicationFiled: May 18, 2016Publication date: September 8, 2016Inventor: Kjeld Svendsen
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Patent number: 9367454Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.Type: GrantFiled: August 15, 2013Date of Patent: June 14, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventor: Kjeld Svendsen
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Patent number: 9336164Abstract: Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.Type: GrantFiled: October 4, 2012Date of Patent: May 10, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventor: Kjeld Svendsen