Abstract: Embodiments relate to a gate driving device including a reference voltage generator for generating a kickback compensating reference voltage, the kickback compensating reference voltage decreasing during one frame section based on a horizontal synchronization signal, and a gate output voltage generator for decreasing a kickback compensating voltage of a gate output voltage during one frame section based on the kickback compensating reference voltage.

Abstract: A liquid crystal display device is provided as follows. A display panel having a first aspect ratio includes pixels, scan lines and data lines. The pixels are arranged at intersections of the scanning lines and the data lines. A display panel driver, in a partial mode in which an image having a second aspect ratio different from the first aspect ratio is displayed on a partial region of the display panel for two or more frame periods, supplies scan signals only to a first number of scan lines electrically connected to pixels of the partial region for a first type frame period of the two or more frame periods, and supplies scan signals to the plurality of scan lines for a second type frame period of the two or more frame periods.

Abstract: A display panel driving apparatus includes a control circuit, a data driver and a gate driver. The control circuit is configured to receive a first control signal for recovering a clock signal from a display signal including image data and the clock signal, and calculate a root mean square of the first control signal to output a second control signal. The data driver is configured to receive the display signal, receive the second control signal, recover the clock signal from the display signal according to the second control signal, and output a data signal based on the image data to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel.

Abstract: A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.

Abstract: A display device and a driving method thereof can reduce or prevent deterioration of image quality caused by ripples of a power voltage. A display device includes a gamma reference voltage generator generating a plurality of gamma reference voltages using a power voltage. A gamma selection signal generator generates a gamma selection signal corresponding to at least one gamma reference voltage among the gamma reference voltages and the power voltage. A gamma data supply unit stores a plurality of gamma data sets and outputs a gamma data set corresponding to the gamma selection signal from among the gamma data sets. A data driver generates a data signal using the gamma data set supplied from the gamma data supply unit and the gamma reference voltages. A display unit includes data lines transmitting the data signal.

Abstract: An exemplary embodiment of present disclosure provides a display device including a first horizontal line, a first delay line, a second delay line, a delay value determiner, and a timing controller. The first horizontal line receives a gate pulse signal (CPV) generated by a gate driver. The first delay line is connected to the first horizontal line to transmit a gate pulse signal received at a first horizontal position as a first delay signal. The second delay line is connected to the first horizontal line to transmit a gate pulse signal received at a second horizontal position as a second delay signal. The delay value determiner generates a horizontal delay signal based on the first delay signal and the second delay signal. The timing controller determines generation times of line latch signals applied to a plurality of data lines based on the horizontal delay signal.

Abstract: A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.

Abstract: Embodiments relate to a gate driving device including a reference voltage generator for generating a kickback compensating reference voltage, the kickback compensating reference voltage decreasing during one frame section based on a horizontal synchronization signal, and a gate output voltage generator for decreasing a kickback compensating voltage of a gate output voltage during one frame section based on the kickback compensating reference voltage.