Patents by Inventor Klaas Bult

Klaas Bult has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9853615
    Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 26, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Md Shakil Akter, Klaas Bult
  • Publication number: 20170302237
    Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).
    Type: Application
    Filed: April 26, 2016
    Publication date: October 19, 2017
    Applicant: BROADCOM CORPORATION
    Inventors: Md Shakil Akter, Klaas Bult
  • Publication number: 20160254820
    Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.
    Type: Application
    Filed: May 7, 2015
    Publication date: September 1, 2016
    Applicant: Broadcom Corporation
    Inventors: Christopher WARD, Klaas Bult, Iniyavan Elumalai
  • Patent number: 9432038
    Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: August 30, 2016
    Assignee: Broadcom Corporation
    Inventors: Christopher Ward, Klaas Bult, Iniyavan Elumalai
  • Patent number: 8971832
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy Van De Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8841963
    Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: September 23, 2014
    Assignee: Broadcom Corporation
    Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20140167989
    Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: Broadcom Corporation
    Inventors: Frank van der GOES, Christopher Ward, Klaas Bult
  • Patent number: 8749410
    Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 10, 2014
    Assignee: Broadcom Corporation
    Inventors: Frank Van Der Goes, Christopher Ward, Klaas Bult
  • Publication number: 20140002194
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Application
    Filed: June 4, 2013
    Publication date: January 2, 2014
    Inventors: Klaas Bult, Rudy Van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8489052
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: July 16, 2013
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8410820
    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 2, 2013
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy Van de Plassche, Jan Mulder
  • Patent number: 8195117
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: June 5, 2012
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Ramon A. Gomez
  • Patent number: 8111095
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 7, 2012
    Assignee: Broadcom Corporation
    Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
  • Publication number: 20110304394
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Application
    Filed: December 6, 2010
    Publication date: December 15, 2011
    Applicant: Broadcom Corporation
    Inventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8045066
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: October 25, 2011
    Assignee: Broadcom Corporation
    Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr, Christopher M. Ward, Ralph Duncan, Tom W. Kwan, James Y. C. Chang, Haideh Khorramabadi
  • Publication number: 20110133967
    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicant: Broadcom Corporation
    Inventors: Klaas BULT, Rudy VAN DE PLASSCHE, Jan MULDER
  • Publication number: 20110067083
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 17, 2011
    Applicant: Broadcom Corporation
    Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr, Christopher M. Ward, Ralph Duncan, Tom W. Kwan, James Y.C. Chang, Haideh Khorramabadi
  • Patent number: 7906992
    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 15, 2011
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy Van de Plassche, Jan Mulder
  • Patent number: 7848724
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 7, 2010
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 7821581
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 26, 2010
    Assignee: Broadcom Corporation
    Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr, Christopher M. Ward, Ralph Duncan, Tom W. Kwan, James Y. C. Chang, Haideh Khorramabadi