Abstract: Binary indications are converted to an analog representation with significant reductions in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. The converter includes pluralities of decoders and latches, each decoder being associated with an individual latch. Each decoder responds to binary indications of an individual row and an individual column and the next column to produce a latched pair of output indications, inverted relative to each other, in synchronism with a clock signal. The production of the latched outputs in synchronism with the clock signal inhibits ringing in the period during each binary indication. Each pair of inverted latch outputs is respectively introduced to a differential amplifier, formed from MOS transistors of the p type, in an individual one of a plurality of current sources.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: A noise-insensitive device for generating a bias current includes a reference voltage source for supplying a reference voltage between a first reference terminal and a second reference terminal. A bias current generator generates the bias current in response to the reference voltage and includes a first and-a second input terminal coupled to the first and the second reference terminal via connecting wires which receive the reference voltage. A first and a second transistor arranged as a differential pair with the gate of the first transistor coupled to the first input terminal and the gate of the second transistor coupled to the second input terminal. The source of the first transistor and the source of the second transistor are coupled to one another at a common terminal for receiving a common current. Each of said transistors has a drain for supplying a first transistor current and a second transistor current, respectively, whose difference decreases when the common current increases.

Abstract: A current divider for linearly dividing a first signal current (Ii10) into a second and a third signal current (Io11, Io12) includes a first terminal (I10) for the passage of the first signal current (Ii10), a second terminal (O11) for the passage of the second signal current (Io11) and for receiving a first potential, a third terminal (O12) for the passage of the third signal current (Io12) and for receiving a second potential, a first MOS transistor (M1) having a control electrode and a main current path, and a second MOS transistor (M2) having a control electrode and a main current path, the control electrodes of the first and the second MOS transistor (M1, M2) being coupled to a first reference terminal (R10) for receiving a first reference voltage (Rv10) to realize a conductive state of the first and the second MOS transistor (M1, M2) during a first active state of the current divider, the main current path of the first MOS transistor (M1 ) being coupled between the first terminal (I10) and the second te

Abstract: An amplifier arrangement comprises a first transistor (N1) having a control electrode coupled to an input terminal for receiving an input signal (Vin), a first main electrode coupled to a first supply-voltage terminal (2), and having a second main electrode. A second transistor (N2) has a control electrode, a first main electrode coupled to the second main electrode of the first transistor, and a second main electrode coupled to a second supply-voltage terminal (3) by means of a current source (J1). An output terminal supplies an output signal (Vout). An amplifier (N4, N5) has an inverting input (V1) coupled to the second main electrode of the first transistor, and an output (V0) coupled to the control electrode of the second transistor.

Abstract: The gain of a cascode amplifier arrangement comprising a first transistor (N1), a second transistor (N2), a current source (J1), an input terminal (1) and an output terminal (3) is increased by adding an amplifier (A) having a non-inverting input (v1), an inverting input (v2) and an output (v0), which are coupled to a reference voltage terminal (2), to the mutually coupled electrodes of the first transistor (N1) and the second transistor (N2), and to the control electrode of the second transistor (N2) respectively. As a result the gain of the arrangement is higher and without a reduction of the unity-gain-bandwidth.