Patents by Inventor Klaas-Jan De Langen
Klaas-Jan De Langen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11520363Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.Type: GrantFiled: September 22, 2020Date of Patent: December 6, 2022Assignee: NXP B.V.Inventors: Antonius Martinus Jacobus Daanen, Klaas-Jan de Langen, Sybren Matthias Bouwhuis
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Patent number: 11456745Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.Type: GrantFiled: September 22, 2020Date of Patent: September 27, 2022Assignee: NXP B.V.Inventors: Klaas-Jan de Langen, Antonius Martinus Jacobus Daanen, Frederik van den Ende
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Patent number: 11424721Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.Type: GrantFiled: October 13, 2020Date of Patent: August 23, 2022Assignee: NXP B.V.Inventors: Gian Hoogzaad, Guillaume Lebailly, Klaas-Jan de Langen
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Publication number: 20210159856Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.Type: ApplicationFiled: October 13, 2020Publication date: May 27, 2021Inventors: Gian Hoogzaad, Guillaume Lebailly, Klaas-Jan De Langen
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Publication number: 20210126638Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.Type: ApplicationFiled: September 22, 2020Publication date: April 29, 2021Inventors: Klaas-Jan de Langen, Antonius Martinus Jacobus Daanen, Frederik van den Ende
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Publication number: 20210124381Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.Type: ApplicationFiled: September 22, 2020Publication date: April 29, 2021Inventors: Antonius Martinus Jacobus Daanen, Klaas-Jan de Langen, Sybren Matthias Bouwhuis
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Patent number: 9953204Abstract: A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures.Type: GrantFiled: January 5, 2017Date of Patent: April 24, 2018Assignee: FINGERPRINT CARDS ABInventors: Rolf Sundblad, Emil Hjalmarson, Erik Säll, Allan Olsson, Klaas-Jan De Langen
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Publication number: 20170308730Abstract: A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures.Type: ApplicationFiled: January 5, 2017Publication date: October 26, 2017Inventors: Rolf Sundblad, Emil Hjalmarson, Erik Säll, Allan Olsson, Klaas-Jan De Langen
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Patent number: 8344740Abstract: The present invention relates to a system for measuring a capacitor (C). A current source (12) is connected in parallel to the capacitor (C) between a supply plane (Vc) and ground (VGND) for providing a current to the capacitor (C). A voltage level-shift is connected between the supply plane (Vc) and the ground (VGND) in parallel to the capacitor (C) and in parallel to the current source (I2). The voltage level-shift senses a voltage across the electronic component (C) and provides a level-shifted output voltage Vout in dependence thereupon. The voltage level-shift comprises a resistor (RI) connected in series with a current source (II) and an output port interposed between the resistor (RI) and the current source (II). The current sources (I,) and (12) have opposite temperature coefficients such that the current provided to the electronic component is substantially constant.Type: GrantFiled: October 28, 2005Date of Patent: January 1, 2013Assignee: NXP B.V.Inventors: Klaas-Jan De Langen, Johan Witte
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Publication number: 20090160459Abstract: The present invention relates to a system for measuring a capacitor (C). A current source (12) is connected in parallel to the capacitor (C) between a supply plane (Vc) and ground (VGND) for providing a current to the capacitor (C). A voltage level-shift is connected between the supply plane (Vc) and the ground (VGND) in parallel to the capacitor (C) and in parallel to the current source (I2). The voltage level-shift senses a voltage across the electronic component (C) and provides a level-shifted output voltage Vout in dependence thereupon. The voltage level-shift comprises a resistor (RI) connected in series with a current source (II) and an output port interposed between the resistor (RI) and the current source (I,). The current sources (I,) and (12) have opposite temperature coefficients such that the current provided to the electronic component is substantially constant.Type: ApplicationFiled: October 28, 2005Publication date: June 25, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Klaas-Jan De Langen, Johan Witte
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Patent number: 7245165Abstract: An amplifier/driver (40) for a bus has an output transistor (M1) that is controlled by a controlled current source (I1). In a quiescent state, the output transistor is configured as part of a current mirror (M1, M11) that maintains a gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing a fast turnon turn-on time. In an active state, the controlled current source provides a substantially constant current to the output transistor to achieve a controlled slew-rate, then reduces the current to the output transistor when a desired output voltage level is achieved. To improve power efficiency, a second controlled current source (I2) provides current to the output load when the desired output voltage level is achieved. To minimize transients, a class-AB control circuit (710) provides a minimum bias current to the output transistor, to prevent it from turning off when the desired output voltage level is achieved.Type: GrantFiled: November 14, 2003Date of Patent: July 17, 2007Assignee: NXP B.V.Inventor: Klaas-Jan De Langen
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Patent number: 7138821Abstract: A digital blocking filter and filtering method are provided for a device receiving signals from a transmission line. The transmission line, which may comprise part of a complex bus system, is incompletely terminated, thereby resulting in a reflection signal within the line with transmission of a signal. The digital blocking filter includes a pulse generator for generating a masking pulse timed and of sufficient duration to substantially block at the device the reflection signal, and logic for combining the masking pulse and a received signal from the transmission line, thereby substantially blocking the reflection signal. Circuitry for handling reflection signals of various duration, as well as for substantially blocking a reflection signal on either a falling edge or a rising edge of a state change in the received signal are provided.Type: GrantFiled: June 30, 2003Date of Patent: November 21, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Edmond Toy, Klaas-Jan De Langen
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Publication number: 20060140285Abstract: A digital blocking filter (120) and filtering method are provided for a device (100) receiving signals from a transmission line. The transmission line, which may comprise part of a complex bus system, is incompletely terminated, thereby resulting in a reflection signal within the line with transmission of a signal. The digital blocking filter (120) includes a pulse generator (140) for generating a masking pulse timed and of sufficient duration to substantially block at the device (100) the reflection signal, and logic (130) for combining the masking pulse and a received signal from the transmission line, thereby substantially blocking the reflection signal. Circuitry for handling reflection signals of various duration, as well as for substantially blocking a reflection signal on either a falling edge or a rising edge of a state change in the received signal are provided.Type: ApplicationFiled: November 15, 2003Publication date: June 29, 2006Applicant: Koninklijke Philips Electronics N.V.Inventors: Edmond Toy, Klaas-Jan De Langen
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Publication number: 20060012411Abstract: An amplifier/driver (40) for a bus has an output transistor (M1) that is controlled by a controlled current source (I1). In a quiescent state, the output transistor is configured as part of a current mirror (M1, M11) that maintains a gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing a fast turnon turn-on time. In an active state, the controlled current source provides a substantially constant current to the output transistor to achieve a controlled slew-rate, then reduces the current to the output transistor when a desired output voltage level is achieved. To improve power efficiency, a second controlled current source (I2) provides current to the output load when the desired output voltage level is achieved. To minimize transients, a class-AB control circuit (710) provides a minimum bias current to the output transistor, to prevent it from turning off when the desired output voltage level is achieved.Type: ApplicationFiled: November 14, 2003Publication date: January 19, 2006Applicant: Koninklijke Philips Electronics N.V.Inventor: Klaas-Jan De Langen
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Publication number: 20060001447Abstract: A level shifting circuit (20, 30) couples an input current (Iin) from one system to another, isolated, system, by driving a single load (L) via one or more current mirrors of a common type. In a first embodiment (20), two similar type (either N-type or P-type) current mirrors (M1,M2;M3,M4) provide output current (Iout1, Iout2) to a common load. Diodes (D1,D2) are used to split the input current (Iin1, Iin2) between the two current mirrors during normal, non-faulty conditions, and to turn off either one of the two current mirrors during a fault condition to permit proper operation in the presence of a fault. In a second embodiment (30), a single current mirror (M1,M2) mirrors the input current (Iin) to the output load (L), and a pair of diodes (D1,D2) selects which of the isolated systems to use as the power source in the event of a fault.Type: ApplicationFiled: November 15, 2003Publication date: January 5, 2006Applicant: Koninklijke Philips Electronics N.V.Inventors: Klaas-Jan De Langen, Balwinder Singh, Edmond Toy
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Publication number: 20050088962Abstract: A digital blocking filter and filtering method are provided for a device receiving signals from a transmission line. The transmission line, which may comprise part of a complex bus system, is incompletely terminated, thereby resulting in a reflection signal within the line with transmission of a signal. The digital blocking filter includes a pulse generator for generating a masking pulse timed and of sufficient duration to substantially block at the device the reflection signal, and logic for combining the masking pulse and a received signal from the transmission line, thereby substantially blocking the reflection signal. Circuitry for handling reflection signals of various duration, as well as for substantially blocking a reflection signal on either a falling edge or a rising edge of a state change in the received signal are provided.Type: ApplicationFiled: June 30, 2003Publication date: April 28, 2005Applicant: Koninklijke Philips Electronics N.V.Inventors: Edmond Toy, Klaas-Jan De Langen
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Patent number: 6542030Abstract: An amplifier comprising an input stage (IPST) having a pair of inputs (INN,INI) for receiving a differential input signal (Vin) and a pair of outputs (CQ6,CQ7) for delivering a differential intermediate signal in response to the differential input signal (Vin); an intermediate stage (INTST) for converting the differential intermediate signal to a non-differential intermediate signal, which intermediate stage (INTST) comprises a current mirror (Q5,R5,Q4,R4) having an input branch (Q5,R5) and an output branch (Q4,R4) for receiving the differential intermediate signal; an output stage (OPST) having an input coupled to the output branch (Q4,R4) and having an output for delivering an output signal (Vout) to an output (OP) of the amplifier; and means for stabilizing the amplifier. The means for stabilizing the amplifier comprises a capacitor (CM2) coupled between the output (OP) of the amplifier and the input branch (Q5,R5), and provides a large bandwidth and low supply voltage amplifier.Type: GrantFiled: September 28, 2001Date of Patent: April 1, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Johan H. Huijsing, Klaas-Jan De Langen
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Patent number: 6452418Abstract: A driving circuit provides a symmetric differential driving signal relative to one set of voltage potentials to a driver circuit that drives an output node to another set of voltage potentials. The differential driving signals from the driving system are equal and opposite to each other, thereby avoiding stray current flow between the driving system and the driven current mirrors. The transistors that provide the driving signal are continuously biased, using a weak bias in one logic state and stronger bias in the other state, to avoid hard-switching transients.Type: GrantFiled: June 28, 2001Date of Patent: September 17, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Balwinder Singh, Klaas-Jan De Langen, Martijn Bredius
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Publication number: 20020063598Abstract: An amplifier comprising an input stage (IPST) having a pair of inputs (INN,INI) for receiving a differential input signal (Vin) and a pair of outputs (CQ6,CQ7) for delivering a differential intermediate signal in response to the differential input signal (Vin); an intermediate stage (INTST) for converting the differential intermediate signal to a non-differential intermediate signal, which intermediate stage (INTST) comprises a current mirror (Q5,R5,Q4,R4) having an input branch (Q5,R5) and an output branch (Q4,R4) for receiving the differential intermediate signal; an output stage (OPST) having an input coupled to the output branch (Q4,R4) and having an output for delivering an output signal (Vout) to an output (OP) of the amplifier; and means for stabilizing the amplifier. The means for stabilizing the amplifier comprises a capacitor (CM2) coupled between the output (OP) of the amplifier and the input branch (Q5,R5), and provides a large bandwidth and low supply voltage amplifier.Type: ApplicationFiled: September 28, 2001Publication date: May 30, 2002Inventors: Johan H. Huijsing, Klaas-Jan De Langen
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Patent number: 6373233Abstract: The present invention provides an LDO that is stable for all capacitive loads. Because the LDO is stable for all capacitive loads, the ESR (equivalent series resistance) inherent in any capacitive load can no longer affect the equivalent value of the combination of the ESR and the capacitive load. Thus, the invention also effectively removes the ESR restrictions on the loads. According to the present invention, a low dropout voltage regulator is provided. The regulator comprises a switching element (e.g., a transistor) having first terminal for receiving an input signal, a second terminal for providing an output signal and a control terminal; a control circuit, operably coupled to the switching element, that is configured to control the switching element; and a compensation circuit having a first segment connected between the first and control terminals of the switching element and a second segment connected between the control and second terminals of the switching element.Type: GrantFiled: December 21, 2000Date of Patent: April 16, 2002Assignee: Philips Electronics No. America Corp.Inventors: Anthonius Bakker, Klaas-Jan de Langen