Abstract: One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor coupled between a second node and the ground voltage; a first n-channel access transistor coupled between a first bit line and the first node of the first inverter, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor; and a second n-channel access transistor coupled between a second bit line and the second node of the second inverter, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor.

Abstract: The invention relates to a semiconductor circuit arrangement having at least one first and a second field effect transistor (T1, T2), where the field effect transistors respectively have at least two active regions (AA11 to AA22) with, respectively, a source region, a drain region and an intermediate channel region, the surface of the channel regions having a gate (G11 to G22) formed on it, insulated by a gate dielectric, for the purpose of actuating the channel regions. At least one active region (AA22) of the second field effect transistor (T2) is arranged between the at least two active regions (AA11, AA12) of the first field effect transistor (T1), which results in a reduced mismatch between the two transistors, caused by temperature and local distances.