Abstract: A computer including a control unit, an arithmetic-logic unit, an input unit, an output unit, a memory unit, and circuitry interconnecting the units for transmitting, processing and storing sequences of characters, the memory unit is constituted by a plurality of stack registers each having a large storage capacity for storing expressions in the form of strings of characters, and the control unit constitutes a reduction processor operatively associated with the stack registers for determining the reducibility, by means of a lambda reduction language, of the expressions stored in the stack registers and for executing any required reductions.

Abstract: In a system for monitoring groups of memory locations in the working memory of a computer equipped with a central processing unit, each location having a capacity of n binary bits, in order to effect automatic location of a group of successive empty locations, which group has a length L at least equal to that required by an interrogating program, and to return a group of memory locations whose contents are no longer required to an unoccupied state and combine such group with following unoccupied groups, there are provided: a memory state register and a base address status register each having a plurality of stages, with each stage corresponding to a respective working memory location and being in one binary state when its corresponding memory location is occupied and in the opposite binary state when its corresponding memory location is empty; an arithmeticlogic function unit including an adder circuit and an indicator circuit connected to the registers for locating a group of successive empty working memory