Abstract: A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

Abstract: A process for forming air-filled isolation trenches in a semiconductor substrate by a conformal chemical vapor deposition (CVD) of a silicon dioxide layer over the passivated surface of the semiconductor substrate in which intersecting trenches have been formed and partially filled with a material that can subsequentially be removed from under the CVD silicon dioxide layer, such materials include water soluble glasses and polymeric materials, such as a polyimide. The CVD silicon dioxide is etched back to the passivated surface of the semiconductor substrate, forming openings in the layer at the trench intersections that extend to the trench fill material. The fill material is removed through these openings. A CVD silicon dioxide layer is deposited to fill the openings, leaving a silicon dioxide cap bridging the air-filled trench. Water soluble glasses that may be used to fill the trench include BSG glass (B.sub.2 O.sub.3 content greater than 55%) and germanosilicate glass (GeO.sub.2 content greater than 50%).

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.

Abstract: A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

Abstract: A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

Abstract: A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: The present invention provides a process which comprises:(a) producing an ion-implantation resistant island on a substrate;(b) growing ion-implantation resistant sidewalls on the island;(c) implanting a first impurity;(d) removing the sidewalls;(e) implanting a second impurity where the sidewalls were;(f) growing a conformal etchable coating over the surface of the device;(g) masking to define an area spaced from and exterior to the area where the sidewalls were;(h) removing the conformal etchable coating in the area of step (g);(i) etching a deep trench in the area where the conformal coating was removed;(j) implanting a third impurity into the deep trench.Following island removal, the emitter and base of a bipolar transistor are formed in the area where the island existed.

Abstract: A cleaning process for a silicon surface, especially a p-type silicon surface. The surface is exposed to HF/H.sub.2 O fumes, thereby obtaining a hexafluosilicic acid film on the surface. The exposed surface is then treated with a water-based, oxidizing, non-silicon-etchant cleaning agent. There is no intermediate rinse between the latter two steps.

Abstract: A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.