Abstract: An oscillator circuit configuration comprising in an LC-parallel oscillatory circuit and a transistor as an amplifying element. A compensating winding is associated with the parallel oscillatory circuit whereby the collector voltage of the transistor is fed to said winding in order to compensate the effect of the parasitic collector capacity. Preferably, the collector current from the transistor is maintained constant be an amplifier.

Abstract: An oscillator circuit configuration comprising in an LC-parallel oscillatory circuit and a transistor as an amplifying element. A compensating winding is associated with the parallel oscillatory circuit whereby the collector voltage of the transistor is fed to said winding in order to compensate the effect of the parasitic collector capacity. Preferably, the collector current from the transistor is maintained constant be an amplifier.

Abstract: The invention relates to an oscillator circuit configuration comprising in an LC-parallel oscillatory circuit and a transistor as an amplifying element. A compensating winding is associated with the parallel oscillatory circuit whereby the collector voltage of the transistor is fed to said winding in order to compensate the effect of the parasitic collector capacity. Preferably, the collector current from the transistor is maintained constant be an amplifier.

Abstract: A frequency arrangement with at least two successive heterodyne stages, one of which converts an input signal with an adjustable first frequency of a superposition oscillator that can be set in fine frequency increments into a first intermediate frequency, a second heterodyne stage that converts an input signal with a fixed second heterodyne frequency of a second superposition oscillator into a second intermediate frequency, the difference frequency between the first and second heterodyne frequencies is converted with an adjustable frequency divider into a lower frequency, which is then compared in a phase detector to the output frequency of a reference oscillator which is implemented as a synthesizer that can be set in fine frequency increments, the first superposition oscillator being synchronized with the output frequency of the reference oscillator via a phase control loop with the output signal of this phase detector, and the adjustable frequency divider preferably being a fractional N-divider with singl

Abstract: The invention relates to dipole and monopole loops with a much shortened emitter relative to the theoretical length thereof and electrically extended at the ends thereof by non-emitting conductor pieces.

Abstract: In a heterodyne stage having a separating filter providing broadband termination for an output of a mixer, a resistance having the value of a system impedance is arranged between the separating filter and a following intermediate-frequency filter, the resistor being interconnected with a resonance element tuned to the intermediate frequency in such a way that the resistor, at the intermediate frequency, has minimal attenuation of the useful signal and, at all other frequencies, terminates the output of the mixer with the system impedance.

Abstract: A frequency arrangement with at least two successive heterodyne stages, one of which converts an input signal with an adjustable first frequency of a superposition oscillator that can be set in fine frequency increments into a first intermediate frequency, a second heterodyne stage that converts an input signal with a fixed second heterodyne frequency of a second superposition oscillator into a second intermediate frequency, the difference frequency between the first and second heterodyne frequencies is converted with an adjustable frequency divider into a lower frequency, which is then compared in a phase detector to the output frequency of a reference oscillator which is implemented as a synthesizer that can be set in fine frequency increments, the first superposition oscillator being synchronized with the output frequency of the reference oscillator via a phase control loop with the output signal of this phase detector, and the adjustable frequency divider preferably being a fractional N-divider with singl

Abstract: A frequency arrangement with at least two successive heterodyne stages, one of which converts an input signal with an adjustable first frequency of a superposition oscillator that can be set in fine frequency increments into a first intermediate frequency, a second heterodyne stage that converts an input signal with a fixed second heterodyne frequency of a second superposition oscillator into a second intermediate frequency, the difference frequency between the first and second heterodyne frequencies is converted with an adjustable frequency divider into a lower frequency, which is then compared in a phase detector to the output frequency of a reference oscillator which is implemented as a synthesizer that can be set in fine frequency increments, the first superposition oscillator being synchronized with the output frequency of the reference oscillator via a phase control loop with the output signal of this phase detector, and the adjustable frequency divider preferably being a fractional N-divider with simpl

Abstract: In an apparatus for EMC testing of electrical devices, conductors are arranged at opposite sides of a chamber of conductive material at a spacing from and parallel to the chamber walls. These conductors form a symmetrical double line and are fed out of phase at one end by a radio frequency source. They are electrically connected to the chamber walls at the other end via terminating impedances.

Abstract: In a reflection-coefficient bridge, the voltage drop across a neutral arm of the bridge is supplied to the indicator via a coaxial cable. The center conductor of the coaxial cable is coupled to the one connecting point of the neutral arm of the bridge while the outer conductor thereof is coupled to the other connecting point thereof. The coaxial cable and a parallel-connected line portion constitute a balanced converter or balun. Both the coaxial cable and the line portion are wound onto at least one ferrite core. A d.c. voltage is fed to a test object, which is connected to the bridge by way of a coaxial line, through a compensating winding wound on at least one of said ferrite cores to the end of the line portion which is r.f. coupled to the frame.

Abstract: In an analyzer for measuring the frequency characteristics of quadripoles, comprising an indicator circuit in which the output of the quadripole to be measured is converted to an intermediate frequency by a mixer and a frequency-variable local oscillator, and comprising a variable-frequency second local oscillator whose output frequency is mixed with another mixer and with the frequency of the local oscillator to be converted to an input signal for the quadripole to be measured, the output frequency of the variable frequency second local oscillator is adjusted to be offset by at least .+-.5 MHz relative to the intermediate frequency value of the indicator circuit.

Abstract: For fast measurement of radio-frequency interference voltages (also called RFI voltages) within a predetermined frequency range in conformity with rating standards, the maximum and minimum peak voltage levels are measured during tuning of the frequency range; when the maximum peak voltage level exceeds a predetermined limit value,the tuning process is interrupted and a quasi-peak measurement is performed at this instantaneous frequency.

Abstract: For a fast and accurate frequency response compensation of a spectrum analyzer, the frequency-dependent control values for controlled amplifier are stored as digital values in a digital memory, and in between the memory and a sweep generator of a heterodyne oscillator, an analog-to-digital converter is disposed to provide frequency-proportional digital values of which the associated frequency-dependent control values stored in a memory can be selected and supplied to the controlled amplifier.