Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.

Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.

Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.

Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.

Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

Abstract: A method for manufacturing a coupled resonator device includes forming a first part of a plurality of layers, trimming an exposed layer of the first part and forming a remaining part of the plurality of layers. The coupled resonator device includes a stack of the plurality of layers, the plurality of layers including a first piezo-layer with a first and a second electrode layer sandwiching the first piezo-layer, a second piezo-layer with a first and a second electrode layer sandwiching the second piezo-layer, the first and second piezo-layers being acoustically coupled to each other.

Abstract: A method for manufacturing a patterned bottom electrode in a piezoelectric device comprises the steps of providing a basic material and producing a layer structure of a conductive material on the basic material. A protective layer is applied on the layer structure over an area. Thereafter, a planarization layer is applied on the protective layer and on the basic material. A portion of the protective layer is then exposed by patterning the planarization layer. Subsequently, the pattern is planarized by removing the portions of the planarization layer remaining outside the portion such that the protective layer laterally abuts on the planarization layer in a flush manner and forms a planar surface. The protective layer is then removed along with a corresponding part of the planarization layer laterally arranged in a flush manner. This results in the layer structure and the remaining planarization layer forming a planar surface.

Abstract: A method for manufacturing a coupled resonator device includes forming a first part of a plurality of layers, trimming an exposed layer of the first part and forming a remaining part of the plurality of layers. The coupled resonator device includes a stack of the plurality of layers, the plurality of layers including a first piezo-layer with a first and a second electrode layer sandwiching the first piezo-layer, a second piezo-layer with a first and a second electrode layer sandwiching the second piezo-layer, the first and second piezo-layers being acoustically coupled to each other.

Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

Abstract: A method for manufacturing a patterned bottom electrode in a piezoelectric device comprises the steps of providing a basic material and producing a layer structure of a conductive material on the basic material. A protective layer is applied on the layer structure over an area. Thereafter, a planarization layer is applied on the protective layer and on the basic material. A portion of the protective layer is then exposed by patterning the planarization layer. Subsequently, the pattern is planarized by removing the portions of the planarization layer remaining outside the portion such that the protective layer laterally abuts on the planarization layer in a flush manner and forms a planar surface. The protective layer is then removed along with a corresponding part of the planarization layer laterally arranged in a flush manner. This results in the layer structure and the remaining planarization layer forming a planar surface.

Abstract: A semiconductor structure including a substrate, a device layer and a contact arranged on the substrate, comprises an ESD protective means, arranged between the substrate and the contact, such, that in the ESD case a breakthrough from the ESD protective means to the contact occurs.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: semiconductor structure having an ESD protective means A semiconductor structure including a substrate (102), a device layer (104) and a contact (108) arranged on the substrate (102), comprises an ESD protective means (144a, 144b), arranged between the substrate (102) and the contact (108), such, that in the ESD case a breakthrough from the ESD protective means (144a, 144b) to the contact (108) occurs.