Patents by Inventor Klaus Dieter McDonald-Maier
Klaus Dieter McDonald-Maier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11133930Abstract: A method for generating an encryption key for use in an encryption process at a device, the method comprising: measuring respective values of a plurality of features of the device to generate a plurality of feature values, normalising the feature values using a respective normalisation map for each feature to generate a plurality of normalised values, and generating the encryption key in dependence on the normalised values.Type: GrantFiled: March 23, 2018Date of Patent: September 28, 2021Assignee: Metrarc LimitedInventors: William Gareth James Howells, Klaus Dieter McDonald-Maier
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Patent number: 11101989Abstract: A method for generating an authentication key for providing a digital signature at a device for authenticating an output from a ring comprising a plurality of peers, the method comprising generating respective security credentials for each peer of a plurality of peers constituting a ring of peers, at least one security credential being generated in dependence on one or more feature of the respective peer device; generating a ring key in respect of the ring in dependence on the respective security credential of each peer constituting the ring; and generating an authentication key in dependence on the ring key, a security credential of a first peer and respective security credentials of at least one of the other peers.Type: GrantFiled: September 24, 2019Date of Patent: August 24, 2021Assignee: Metrarc LimitedInventors: Klaus Dieter McDonald-Maier, William Gareth James Howells, Ruhma Tahir
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Publication number: 20200382295Abstract: A method for generating an encryption key for use in an encryption process at a device, the method comprising: measuring respective values of a plurality of features of the device to generate a plurality of feature values, normalising the feature values using a respective normalisation map for each feature to generate a plurality of normalised values, and generating the encryption key in dependence on the normalised values.Type: ApplicationFiled: March 23, 2018Publication date: December 3, 2020Inventors: William Gareth James Howells, Klaus Dieter McDonald-Maier
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Publication number: 20200099521Abstract: A method for generating an authentication key for providing a digital signature at a device for authenticating an output from a ring comprising a plurality of peers, the method comprising generating respective security credentials for each peer of a plurality of peers constituting a ring of peers, at least one security credential being generated in dependence on one or more feature of the respective peer device; generating a ring key in respect of the ring in dependence on the respective security credential of each peer constituting the ring; and generating an authentication key in dependence on the ring key, a security credential of a first peer and respective security credentials of at least one of the other peers.Type: ApplicationFiled: September 24, 2019Publication date: March 26, 2020Inventors: Klaus Dieter McDonald-Maier, William Gareth James Howells, Ruhma Tahir
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Patent number: 9928361Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: GrantFiled: June 8, 2017Date of Patent: March 27, 2018Assignee: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter McDonald-Maier
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Patent number: 9927486Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: GrantFiled: August 19, 2016Date of Patent: March 27, 2018Assignee: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter Mcdonald-Maier
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Publication number: 20170277883Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: ApplicationFiled: June 8, 2017Publication date: September 28, 2017Applicant: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter McDonald-Maier
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Patent number: 9703944Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: GrantFiled: July 9, 2013Date of Patent: July 11, 2017Assignee: ULTRASOC TECHNOLOGIES LTD.Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter McDonald-Maier
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Publication number: 20160356841Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Applicant: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter Mcdonald-Maier
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Patent number: 9448805Abstract: The invention relates to the method of prefetching data in micro-processor buffer under software controls.Type: GrantFiled: June 14, 2013Date of Patent: September 20, 2016Assignee: COMSATS Institute of Information TechnologyInventors: Muhammad Yasir Qadri, Nadia Nawaz Qadri, Klaus Dieter McDonald-Maier
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Publication number: 20140372730Abstract: The invention relates to the method of prefetching data in micro-processor buffer under software controls.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Muhammad Yasir Qadri, Nadia Nawaz Qadri, Klaus Dieter McDonald-Maier
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Publication number: 20140372735Abstract: The invention relates to the method of prefetching instruction in micro-processor buffer under software controls.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Muhammmad Yasir Qadri, Nadia Nawaz Qadri, Klaus Dieter McDonald-Maier
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Publication number: 20140013421Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.Type: ApplicationFiled: July 9, 2013Publication date: January 9, 2014Inventors: Andrew Brian Thomas Hopkins, Arnab Banerjee, Stephen John Barlow, Klaus Dieter McDonald-Maier
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Patent number: 8112677Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.Type: GrantFiled: February 26, 2010Date of Patent: February 7, 2012Assignee: UltraSoc Technologies LimitedInventors: Stephen John Barlow, Andrew James Bower, Andrew Brian Thomas Hopkins, Klaus Dieter McDonald-Maier
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Publication number: 20110214023Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: UltraSoC Technologies LimitedInventors: Stephen John Barlow, Andrew James Bower, Andrew Brian Thomas Hopkins, Klaus Dieter McDonald-Maier
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Publication number: 20090057914Abstract: A semiconductor device has first and second semiconductor chips comprising electronic circuit elements located at an inner part of the chip and first connection terminals located on an upper surface of the inner part of the chip. One of the chips has second connection terminals located at a peripheral part of the chip. The first and second semiconductor chips are mounted one on top of the other to form the device connected together by the first connection terminals of the first and second semiconductor chips, and wherein the second connection terminals of the first semiconductor chip provide external connections to the device. The invention enables SoC resources to be increased based on the System-in-Package (SiP) approach by duplication identical chip components into a single package.Type: ApplicationFiled: July 22, 2005Publication date: March 5, 2009Applicant: UNIVERSITY OF KENTInventors: Klaus Dieter McDonald-Maier, Andrew Brian Thomas Hopkins