Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Abstract: A method is disclosed by means of which contact holes (K1), (K2) and (K3), leading to integrated components can be produced with just one structuring mask, whereby contact holes (K1) and (K3) lead to contact regions (25e, 45e) in the substrate (5) and contact holes (K2) lead to contact regions (35c, 50c) located on layer stacks (35, 50). An auxiliary layer is used for the etching of contact holes (K1), (K2), (K3), which covers a part of the contact holes and thus serves as a selection mask. The auxiliary layer can be structured with a low-resolution lithography in comparison with the mask, such that only one single high-resolution lithography is necessary for the formation of all contact holes (K1), (K2), (K3). The method is particularly suitable for the simultaneous production of contact holes for transistors in the cell field and the logic field of a DRAM.

Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA?; AA?;) are provided. said sub-structures (STI; AA; AA?; AA?,) having a first sub-structure (AA?) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA?). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.

Abstract: A method is disclosed by means of which contact holes (K1), (K2) and (K3), leading to integrated components can be produced with just one structuring mask, contact regions (25e, 45e) in the substrate (5) and contact holes (K2) lead to contact regions (35c, 50c) located on layer stacks (35, 50). An auxiliary layer is used for the etching of contact holes (K1), (K2), (K3), which covers a part of the contact holes and thus serves as a selection mask. The auxiliary layer can be structured with a low-resolution lithography in comparison with the mask, such that only one single high-resolution lithography is necessary for the formation of all contact holes (K1), (K2), (K3). The method is particularly suitable for the simultaneous production of contact holes for transistors in the cell field and the logic field of a DRAM.

Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: A trench capacitor is formed in a substrate and includes a trench having an upper region and a lower region. An insulating collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A buried plate is formed around the lower region of the trench as an outer capacitor electrode. A dielectric layer, which forms the capacitor dielectric, lines the lower region of the trench and the insulating collar. A conductive trench filling is put into the trench. A conductive contact layer of tungsten nitride is provided above the insulating collar, between the substrate and the conductive trench filling, and acts as a diffusion barrier. This makes it possible to provide the trench capacitor more closely to the transistor, since the transistor is not damaged by material which is contained in the conductive trench filling.

Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.

Abstract: A contact between a polycrystalline silicon structure and a monocrystalline silicon region is produced by doping the silicon structure in amorphous or polycrystalline form and/or doping the monocrystalline silicon region with a dopant, in particular with oxygen, in such a concentration that a solubility limit is exceeded. In a subsequent heat treatment, dopant precipitations are formed which either control grain growth in the polycrystalline silicon layer or prevent a propagation of crystal faults into a substrate in the monocrystalline silicon region. Such a contact can be used, in particular, as a buried strap in a DRAM trench cell.

Abstract: A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.