Abstract: A three-stage non-blocking switching array having twice the number of inputs and outputs for its sub-arrays of its input and output stages as the number of lines to be switched, and having one more sub-array in its intermediate stage than the minumum required to form a non-blocking switching array. The additional or redundant inputs and outputs are connected with the non-redundant inputs and outputs such that the redundant inputs are each individually connected with a non-redundant input of a respective other sub-array of the same respective stage. This construction maintains the non-blocking characteristic of the switching array even if one of the sub-arrays fails since, in such use, redundant substitute paths are available.