Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.

Abstract: The invention encompasses resistors comprising a thin layer of dielectric material and methods of forming such resistors. The invention also encompasses integrated circuitry comprising such resistors, including SRAM circuitry, and encompasses methods of forming such integrated circuitry. In one aspect, the invention includes a resistor construction for electrically connecting a first node location to a second node location comprising: a) a first conductive layer in electrical connection with the first node location; b) a second conductive layer in electrical connection with the second node location; and c) a dielectric material intermediate the first conductive layer and the second conductive layer and having a thickness of from about 15 Angstroms to about 60 Angstroms.

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: A capacitor and a method for forming a capacitor is described and which includes providing a node location to which electrical connection to a capacitor is to be made; providing an amorphous inner capacitor plate layer of a first material atop the node location; providing a capacitor dielectric layer outwardly of the first material; after providing the capacitor dielectric layer, rendering the first material to be polycrystalline; providing an electrically conductive outer capacitor plate layer outwardly of the capacitor dielectric layer; and providing the first material to be electrically conductive. The capacitor formed by the present method exhibits current leakage characteristics which are substantially symmetrical with respect to both positive and negative voltage bias and characterized by differences between the positive and negative voltage bias being within less than about 10 percent for a predetermined voltage.

Abstract: A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon portion of the polycide line is formed after formation of the metal siticide portion. The formation of the metal silicide portion of the polycide structure may include forming an oxide hard mask over the polysilicon layer exposing line portions of the polysilicon layer. The exposed line portions of the polysilicon layer are silicided resulting in a refractory metal silicide portion and unreacted material over the oxide hard mask. The unreacted material and oxide hard mask are then removed. The refractory metal silicide portion may be formed by forming a refractory metal or metal silicide layer, such as cobalt or cobalt silicide, over the oxide hard mask and exposed portions of the polysilicon layer.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: A capacitor construction includes, i) a dense mass of electrically insulative oxide; ii) an electrically conductive inner capacitor plate overlying and contacting the electrically insulative oxide mass; iii) a capacitor dielectric layer overlying the inner capacitor plate and oxide mass, the capacitor dielectric layer comprising a nitride; iv) an electrically conductive outer capacitor plate overlying the capacitor dielectric layer; and v) the dense mass of electrically insulative oxide contacting the inner capacitor plate being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: A capacitor and a method for forming a capacitor is described and which includes providing a node location to which electrical connection to a capacitor is to be made; providing an amorphous inner capacitor plate layer of a first material atop the node location; providing a capacitor dielectric layer outwardly of the first material; after providing the capacitor dielectric layer, rendering the first material to be polycrystalline; providing an electrically conductive outer capacitor plate layer outwardly of the capacitor dielectric layer; and providing the first material to be electrically conductive. The capacitor formed by the present method exhibits current leakage characteristics which are substantially symmetrical with respect to both positive and negative voltage bias and characterized by differences between the positive and negative voltage bias being within less than about 10 percent for a predetermined voltage.

Abstract: A capacitor construction includes, i) a dense mass of electrically insulative oxide; ii) an electrically conductive inner capacitor plate overlying and contacting the electrically insulative oxide mass; iii) a capacitor dielectric layer overlying the inner capacitor plate and oxide mass, the capacitor dielectric layer comprising a nitride; iv) an electrically conductive outer capacitor plate overlying the capacitor dielectric layer; and v) the dense mass of electrically insulative oxide contacting the inner capacitor plate being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution.