Abstract: The present invention pertains to novel treatments of neuropathic pain; in particular chemotherapy induced peripheral neuropathic pain (CIPNP). The invention provides antagonists cytochrome P450 epoxygenases (CYP), and more specifically antagonists of CYP2J2, as therapeutics for use in the treatment of neuropathic pain such as CIPNP. CYP2J2 antagonists were identified to alleviate CIPNP in-vivo, and therefore are provided additionally in combination with chemotherapeutics for the treatment of diseases such as cancer or other proliferative disorders. The CYP2J2 antagonists reduce chemotherapeutic induced pain and therefore allow for a higher dosing of the chemotherapeutic during cancer treatment. In addition the invention relates to the use of CYP2J2 agonists, or metabolites of CYP2J2, for sensitizing TRPV1.

Abstract: A method is disclosed for transmission of register contents of a CT detector with hierarchical hardware structure, wherein the first hierarchy level is formed by a control unit containing a register table for the read-out register contents of FPGAs lying lower down in the hierarchy and an intermediate register store for register contents to be written. With each new reading, the new register contents for FPGAs lying lower down in the hierarchy arriving during the respective preceding reading from the central control at the control unit are forwarded to the next hierarchy level. With each new reading, the register contents of all FPGAs lying lower down in the hierarchy are re-entered into the register table of the control unit. Finally, in the event of a readout command transferred asynchronously from the central control, the register contents are read out exclusively from the register table.

Abstract: A method is disclosed for transmission of register contents of a CT detector with hierarchical hardware structure, wherein the first hierarchy level is formed by a control unit containing a register table for the read-out register contents of FPGAs lying lower down in the hierarchy and an intermediate register store for register contents to be written. With each new reading, the new register contents for FPGAs lying lower down in the hierarchy arriving during the respective preceding reading from the central control at the control unit are forwarded to the next hierarchy level. With each new reading, the register contents of all FPGAs lying lower down in the hierarchy are re-entered into the register table of the control unit. Finally, in the event of a readout command transferred asynchronously from the central control, the register contents are read out exclusively from the register table.

Abstract: An apparatus for the acquisition of items of identity information (19/31), in particular for the measurement of sport time and/or for monitoring and possibly invoicing in the course of access checks or operations involving transportation of material, is to be designed to be as manipulation-resistant as possible. For that purpose a distinction is made between local acquisition regions, in each of which is installed at least one reading device (22), and at least one central processing region which is operated separately therefrom and under special control and at which an evaluation device (43) is operated. The transfer of data between the acquisition region and the processing region is effected so-to-speak `physically` by means of an operating device (30) which can only be connected either to the reading device (22) or to the evaluation device (43).

Abstract: A remote control for a locking device, especially in a motor vehicle, including a control or operating unit for the transmitting of key words to the evaluating circuit of a reading unit fora comparison with key words which are stored therein. The remote control arrangements are equipped with counters for the call-up in a system-time controlled manner of the key words which are stored in the control and reading units.

Abstract: A circuit arrangement for the implementation of a fast discrete Fourier transform in real time through the controlled operation of cross-linked butterfly, or kernel, operators. The circuit arrangement will successively transmit the two halves of a sequence of complex input words through a series-parallel input register and an interim data storage to a plurality of butterfly operators which operate in parallel, whose outputs are switchable by a multiplexer for recursive linkage with the interim storage or, in essence, for the delivery of the frequency range-output words to a parallel-series output register.