Abstract: Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Abstract: To ensure error-free transmission of digital information, very stringent requirements are placed on the accuracy and stability of the clock generators. It is known to use microprocessor-controlled digital phase-locked loops for this purpose, which contain costly high-stability crystal oscillators. An accurate system clock signal is to be provided even if the reference clock signal fails. Contradictory requirements are placed on the phase-locked loops, namely, on the one hand, a wide bandwidth to achieve a small time interval error, and, on the other hand, a narrow bandwidth to minimize the effect of jitter and wander on clock accuracy if the reference clock signal should fail. The invention provides a circuit arrangement for a low-cost clock generator which generates a highly accurate clock frequency even in the event of a failure of the reference clock signal.

Abstract: A digital phase comparator measures the phase difference of two signals (S1, S3) from a third signal (S2), and calculates the difference. The zero crossing of the two signals respectively sets two flip-flops (11, 12). If both flip-flops are set, they are simultaneously reset with a delay. Each set flip-flop enables a corresponding counter (13, 14). An evaluation unit averages the counter outputs at major intervals. The phase comparator can be incorporated into a phase-locked loop.

Abstract: The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.