Abstract: Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage (101; 301), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit (201; 320), the first single bit storage including at least a first output (A; A0) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0) and two field effect transistors (113, 114; 312, 313). In order to reduce the power consumption, the first output (A; A0) of the single bit storage (101; 301) is applied to the gate of only one, a first field effect transistor (114; 312) of the two field effect transistors (113, 114; 312, 313). For an additional reduction of the power consumption, two single bit storages (101, 301) are connected to a shared compare circuit (319).

Abstract: Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage (101; 301), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit (201; 320), the first single bit storage including at least a first output (A; A0) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0) and two field effect transistors (113, 114; 312, 313). In order to reduce the power consumption, the first output (A; A0) of the single bit storage (101; 301) is applied to the gate of only one, a first field effect transistor (114; 312) of the two field effect transistors (113, 114; 312, 313). For an additional reduction of the power consumption, two single bit storages (101, 301) are connected to a shared compare circuit (319).

Abstract: In order to provide a more efficient method and system for data lookups, it is proposed to provide the known CAM (100) with an additional comparator (301). The comparator (301) does not comprise a memory circuit and therefore allows a faster comparison of input data (D0 to D31) with compare data (C0 to C31) than the known compare circuit (106). In addition, it is proposed to temporarily inhibit forwarding of the output signal of the specific CAM circuit into which the input data (D0 to D31) are written, in order to avoid forwarding of a wrong match signal to the data processing system.

Abstract: A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).

Abstract: In order to provide a more efficient method and system for data lookups, it is proposed to provide the known CAM (100) with an additional comparator (301). The comparator (301) does not comprise a memory circuit and therefore allows a faster comparison of input data (D0 to D31) with compare data (C0 to C31) than the known compare circuit (106). In addition, it is proposed to temporarily inhibit forwarding of the output signal of the specific CAM circuit into which the input data (D0 to D31) are written, in order to avoid forwarding of a wrong match signal to the data processing system.

Abstract: A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).

Abstract: The invention relates to a contents-addressable memory (CAM) with multiple logical-memory arrays Di. The logical-memory arrays Di are distributed logically in multiple blocks Dij. The blocks Dij are physically arranged to memory arrays Di' and integrated on the chip surface. Each memory array Di' hereby has one block Dij of the logical memory arrays Di. In this way, parasitic capacities of the CAM may be minimized.

Abstract: A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.

Abstract: A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.

Abstract: A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit.