Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

Abstract: Signal routing using structures based on buried power rails (BPRs) is described. An example IC device includes a support structure, a plurality of IC components provided over the support structure, and first and second electrically conductive structures having respective portions that are buried in the support structure, such structures referred to as “buried signal rails” (BSRs). The first BSR may be electrically coupled to a terminal of one of the plurality of IC components, the second BSR may be electrically coupled to a terminal of another one of the plurality of IC components, and the IC device may further include a bridge interconnect embedded within the support structure, the bridge interconnect having a first end in contact with the first BSR and a second end in contact with the second BSR. Implementing BSRs in IC devices may allow significantly increasing standard cell library density and provide geometry-free signal routing.

Abstract: A semiconductor die is provided. The semiconductor die comprises a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure. A top surface of the electrically conductive structure is contacted at the front side of the semiconductor substrate and a bottom surface of the electrically conductive structure is contacted at a backside of the semiconductor substrate. Further, the semiconductor die comprises a backside metallization layer stack attached to the backside of the semiconductor substrate. A first portion of a wiring structure is formed in a first metallization layer of the backside metallization layer stack and a second portion of the wiring structure is formed in a second metallization layer of the backside metallization layer stack.

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.

Abstract: Lithography masks and methods of lithography for manufacturing semiconductor devices are disclosed. Forbidden pitches are circumvented by dividing a main feature into a set of two or more sub-features. The sum of the widths of the sub-features and the spaces between the sub-features is substantially equal to the width of the main feature. The set of two or more sub-features comprise a plurality of different distances between an adjacent set of two or more sub-features. At least one of the plurality of distances comprises a pitch that is resolvable by the lithography system, resulting in increased resolution for the main features, improved critical dimension (CD) control, and increased process windows.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Abstract: Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.