Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.

Abstract: A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).

Abstract: Semiconductor structures and methods of fabrication are provided. One semiconductor structure includes a substrate, a semiconductor device layer supported by the substrate, and one or more buried through substrate vias (TSVs) disposed at least partially within the substrate. The buried through substrate via(s) is buried within the semiconductor substrate, and terminates below the semiconductor device layer of the semiconductor structure, and the semiconductor device layer extends over the buried through substrate via(s), thereby providing the buried through substrate via(s) without consuming space within the semiconductor device layer. A dielectric layer may be disposed between the substrate and the semiconductor device layer, with the TSV(s) terminating at a first end within the dielectric layer. Alternatively, the semiconductor device layer may be an epitaxially-grown layer extending over the TSV(s).

Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.

Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of the semiconductor wafer. The method includes redistributing signals from the wafer bond pads to redistribution edge pads utilizing the redistribution layer, and routing signals from the semiconductor wafer up to the redistribution layer and routing these signals back down to the semiconductor wafer.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.