Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp, address and data values. The transaction record information is stored/captured on a high level-based (i.e., system address-based) domain that takes into account all the tiling, interleaving, scrambling, and unaligned accessing used in the simulated SOC design, rather than on a low level-based (i.e., physical memory address-based) domain. Upon completing the simulation, the instantaneous memory contents at any selected point in time during the simulated execution are calculated by combining the initial data and intermediate transaction record information. Automatic memory dump and sanity check tests verify the integrity of the final data value and incremental transactions.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: A microprocessor system includes an address generator, an address selector, and memory system having multiple memory towers, which can be independently addressed. The address generator simultaneously generates a first memory address and a second memory address that is 1 row greater than the first memory address. The address selector determines whether the row portion of the first memory address or the second memory address is used for each memory tower. Because each tower can be addressed independently, a single memory access can be used to access data spanning multiple rows of the memory system.

Abstract: An embedded processor architecture includes a processing core with configurable memory system. Memory components can be inserted, omitted and resized in different configuration of the memory system without causing irregular features that may cause wasted silicon area. Furthermore, all the various configurations of the memory system are designed to interface with the processing core so that the processing core can be reused without change.

Abstract: A load/store pipeline uses a store buffer pipeline to avoid data dependency issues and resource conflicts. Store instructions are stored in the store buffer pipeline. During processing of a later store instruction, the stored instruction stores data into the memory system. Specifically the stored store instruction stores data during the same load/store pipeline stage that a load instruction would read data from the memory system. Thus, memory resource conflicts caused by a store instruction followed by a load instruction are avoided. Some embodiments of the present invention includes N store buffer stages so that a first store instruction is not carried out until the (N+1)th store instruction is processed. The delay provided by the store buffer pipeline can be used to process information regarding the store instruction such as cache hits or misses and store cancellation instructions.