Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.

Abstract: A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches (116) of a workpiece (112). A temporary spacer adjacent gate electrode contacts (132) and pad nitride layer are removed. A spacer material is deposited over exposed portions of the workpiece (112) and over the top and sides of the gate electrode contacts (132). The spacer material is removed from the horizontal surfaces of the DRAM device (100), including the exposed portions of the workpiece (112) and the top of the gate electrode contacts (132). Spacers (144) having sidewalls sloping downwardly away from the gate electrode contacts (132) are left remaining on the gate electrode contact (132) sides, preventing voids from forming during a subsequent array top oxide deposition. Spacers may also be formed adjacent top regions of isolation trenches simultaneously with the formation of spacers (144).

Abstract: A method of manufacturing a vertical DRAM device (10) having isolation trenches (38) with a controlled height. A support liner (54) is disposed over support regions (18) of a wafer. A first insulating layer is disposed over the wafer, and the first insulating layer is removed from a top surface of the wafer, leaving a portion (52) of the first insulating layer disposed over at least the array region (16). The isolation trenches (38) may be recessed below a top surface of the wafer pad nitride (14), so that portions of the first insulating layer (52) are left remaining over the support liner (54) over the support region isolation trenches (38).

Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133).