Patents by Inventor Klaus M. Kroener
Klaus M. Kroener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10649738Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.Type: GrantFiled: April 10, 2019Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
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Patent number: 10649730Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: GrantFiled: June 26, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Patent number: 10459689Abstract: Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.Type: GrantFiled: June 10, 2015Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Silvia Melitta Mueller, Manuela Niekisch, Kerstin Schelm
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Publication number: 20190317726Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Inventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Patent number: 10416962Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.Type: GrantFiled: October 2, 2015Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Juergen Haess, Michael Klein, Klaus M. Kroener, Petra Leber, Silvia M. Mueller, Kerstin Schelm
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Patent number: 10379811Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: GrantFiled: November 16, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Publication number: 20190235841Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
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Patent number: 10303438Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.Type: GrantFiled: January 16, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tina Babinsky, Udo Krautz, Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10303440Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.Type: GrantFiled: January 19, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
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Patent number: 10235135Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: GrantFiled: July 17, 2017Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Publication number: 20190018648Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Klaus M. KROENER, Cedric LICHTENAU, Silvia M. MUELLER, Andreas WAGNER
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Publication number: 20190018649Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: ApplicationFiled: November 16, 2017Publication date: January 17, 2019Inventors: Klaus M. KROENER, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Patent number: 10095475Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: GrantFiled: December 13, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20180203667Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.Type: ApplicationFiled: January 16, 2017Publication date: July 19, 2018Inventors: Tina BABINSKY, Udo KRAUTZ, Klaus M. KROENER, Silvia M. MUELLER, Andreas WAGNER
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Publication number: 20180203672Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.Type: ApplicationFiled: January 19, 2017Publication date: July 19, 2018Inventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
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Patent number: 9959093Abstract: A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.Type: GrantFiled: June 29, 2016Date of Patent: May 1, 2018Assignee: International Business Machines CorporationInventors: Michael Klein, Klaus M. Kroener, Cédric Lichtenau, Silvia Melitta Mueller
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Patent number: 9952829Abstract: A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.Type: GrantFiled: February 1, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Michael Klein, Klaus M. Kroener, Cédric Lichtenau, Silvia Melitta Mueller
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Publication number: 20180101358Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: ApplicationFiled: December 13, 2017Publication date: April 12, 2018Inventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Patent number: 9870200Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: GrantFiled: November 17, 2016Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Patent number: 9767073Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.Type: GrantFiled: June 8, 2015Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller, Kerstin Schelm