Abstract: Embodiments of the invention relate to an apparatus and a method for testing a plurality of devices under test. The apparatus for testing a plurality of devices under test comprises a common device output line and a driver unit configured to provide a stimulus to the DUTs. The driver unit is configured such that the stimulus reaches different DUTs at different times, thereby creating stimuli time shifts at the DUTs. The apparatus further comprises a receiver unit electrically coupled to the common device output line and a plurality of DUTs connections, electrically coupled to the common device output line, so that DUT terminals of the plurality of DUTs are electrically coupleable via the common device output line to the receiver unit.

Abstract: Embodiments of the invention relate to an apparatus and a method for testing a plurality of devices under test. The apparatus for testing a plurality of devices under test comprises a common device output line and a driver unit configured to provide a stimulus to the DUTs. The driver unit is configured such that the stimulus reaches different DUTs at different times, thereby creating stimuli time shifts at the DUTs. The apparatus further comprises a receiver unit electrically coupled to the common device output line and a plurality of DUTs connections, electrically coupled to the common device output line, so that DUT terminals of the plurality of DUTs are electrically coupleable via the common device output line to the receiver unit.

Abstract: A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested.

Abstract: A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested.

Abstract: There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining a timing control signal on the base of the first clock signal and the second signal, generating an adjusted clock signal by adjusting the timing of the first clock signal corresponding to the timing control signal, and using the adjusted clock signal for sampling a signal received from the second unit. The second signal is a clock signal received from the second unit, the adjusted clock signal is used for sampling this clock signal itself, and a corresponding sampled clock signal is supervised to show proper clock functionality.

Abstract: The invention relates to source synchronous sampling by synchronizing a first clock signal of a first unit to a data signal received from a second unit, comprising the steps of measuring a phase difference between the first clock signal and a second signal, and generating a corresponding timing control signal, generating an adjusted clock signal by adjusting the timing of the first clock signal corresponding to the timing control signal, and generating sampled data by using the adjusted clock signal for sampling the received data signal.

Abstract: A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested.

Abstract: A testing unit (10) for testing a device under test—DUT—(30) comprises a signal generator (20) for applying a stimulus signal to the DUT (30), a receiving unit (50) for receiving a response signal from the DUT on the applied stimulus signal, and a synchronizing unit (40) for synchronizing a data flow of the response signal between the DUT (30) and the receiving unit (50). The synchronizing unit (40) receives a first clock signal (DUT-CLK) from the DUT (30) and a second clock signal (CLK) of the testing unit (10). The synchronizing unit (40) comprises a buffer (70) for buffering data, a write unit (80) for writing data from the DUT (30) into the buffer (70), and a read unit (90) for reading out data from the buffer (70) to be provided to the receiving unit (50). A write access onto the buffer (70) is controlled by the first clock signal (DUT-CLK), while a read access onto the buffer (70) is controlled by the second clock signal (CLK).

Abstract: An apparatus for testing an electronic device, in particular an integrated circuit tester and specifically designed for testing memories or logic/memory combinations, provides a multiplicity of pin channels. Each pin channel includes a sequence controller communicating with a decompression control unit. This combination is extremely fast and allows to designate the respective pin channels to an address or a data pin of a memory or to a logic pin of a device under test. A central controller provides the necessary control instructions to instruction memories of the sequence controllers. All sequence controllers assigned to a logic pin execute basically the same program, wherein pin adaptation is performed by a vector memory. In contrast, sequencers assigned to an address pin execute different, pin-specific instructions. The architecture may be easily adapted to varying pin definitions and is based on the "per pin resource" approach. It may also be applied to board testers and other electronic testing devices.

Abstract: An apparatus for generating test signals, preferably for use in an integrated circuit tester, comprises a sequencer, a Vector Memory and a Waveform Memory. The Vector Memory is addressed by the sequencer and contains coded waveform information, which is, in turn, decoded into control information by the Waveform Memory. For this purpose, the data outputs of the Vector Memory control the address inputs of the Waveform Memory. The data outputs of the Waveform Memory control circuitry like a formatter or a comparator which link the waveform information with timing information from one or more edge generators. The formatters, comparators etc. are, in turn, in connection with a device under test. The present apparatus provides full flexibility in the generation of formats and waveforms and, in particular, timing and format changes "on the fly", i.e. without additional delay. Flexibility may be increased if the Waveform Memory is reprogammable.