Abstract: A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing.

Abstract: The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone.

Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

Abstract: A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.

Abstract: The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone.

Abstract: A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

Abstract: A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.